Scenario: Gen5 EQ Failure After Retimer FW Update

Scenario

A platform passes Gen4 compliance and cold-boot Gen5 training, but after a retimer firmware update Gen5 link intermittently drops to Gen4 during sustained DMA. LTSSM logs show repeated Recovery entry after EQ phase 3 timeouts on lanes 8-15.

OBSERVED METRIC
Gen5 link stability with Recovery loop frequency and EQ phase 3 timeout rate on upper lane group.

45-MINUTE INTERVIEW FLOW
0-5: scope traffic and SLA context
5-15: map first failing PCIe/CXL layer
15-25: identify proving artifacts
25-35: propose bounded fix with owner
35-45: state validation matrix and rollback

Common pitfalls

• Blame endpoint PHY without capturing retimer ordered sets and preset feedback.

• Re-run compliance once at room temp without corner or traffic stress.

• Force Gen5 by disabling downgrade without proving EQ margin headroom.

Scenario debrief

Score candidate response on traffic framing, timing proof, mitigation boundedness, and regression discipline.

request stream -> controller policy -> PCIe/CXL timing behavior -> measured outcome

latency/bandwidth trend

Debrief prompts

1. Which PCIe/CXL timing or queue behavior fails first in evidence?

2. Which smallest safe controller, PHY, or policy change addresses it?

3. Which benchmark + counter gate proves closure under production traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing PCIe/CXL captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.