Scenario: Rare Stale Read Under CXL.cache Contention

Scenario

A Type 2 accelerator passes functional tests but production ML jobs rarely produce wrong logits when CPU threads concurrently update shared embedding tables. Coherency traces show delayed invalidations during ownership upgrades under high snoop pressure.

OBSERVED METRIC
Coherency litmus failure rate and ownership upgrade retry latency under mixed CPU/device writers.

45-MINUTE INTERVIEW FLOW
0-5: scope traffic and SLA context
5-15: map first failing PCIe/CXL layer
15-25: identify proving artifacts
25-35: propose bounded fix with owner
35-45: state validation matrix and rollback

Common pitfalls

• Close on average bandwidth without litmus and ownership traces.

• Treat as application bug without checking fence and ordering contracts.

• Disable snoop paths to improve performance without understanding RAS impact.

Scenario debrief

Score candidate response on traffic framing, timing proof, mitigation boundedness, and regression discipline.

request stream -> controller policy -> PCIe/CXL timing behavior -> measured outcome

latency/bandwidth trend

Debrief prompts

1. Which PCIe/CXL timing or queue behavior fails first in evidence?

2. Which smallest safe controller, PHY, or policy change addresses it?

3. Which benchmark + counter gate proves closure under production traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing PCIe/CXL captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.