PCIe/CXL Deep Dive · All levels
CXL Protocols and Device Types: Tricky Q&A
Senior interview and review questions for CXL Protocols and Device Types.
Section Q&A bank
Use these drills after completing all topics in CXL Protocols and Device Types. Answer with workload context, mechanism proof, artifact, owner, and release decision.
Why must CXL.io enumerate cleanly before enabling CXL.cache?
diagram
[INT][PCIE-CXL][CXL-PROTOCOLS]
Q: Why must CXL.io enumerate cleanly before enabling CXL.cache?
A:
CXL.cache depends on mailbox negotiation, DVSEC capabilities, and coherency parameters established during CXL.io bring-up. Skipping steps leaves undefined cache geometry and risks host coherence violations.
FOLLOW-UP TRAP: Enabling cache protocol before mailbox reports supported coherency mode.How does CXL.cache differ from software-managed DMA coherence?
diagram
[INT][PCIE-CXL][CXL-PROTOCOLS]
Q: How does CXL.cache differ from software-managed DMA coherence?
A:
CXL.cache participates in hardware coherency with snoops and state transitions; DMA coherence relies on explicit flush/invalidate sequences. Mixing models without clear domain boundaries causes stale data bugs.
FOLLOW-UP TRAP: Treating CXL.cache devices like ordinary PCIe DMA endpoints.What HDM programming is required before OS sees CXL.mem capacity?
diagram
[INT][PCIE-CXL][CXL-PROTOCOLS]
Q: What HDM programming is required before OS sees CXL.mem capacity?
A:
Firmware must program HDM decoders, publish region base/size, and coordinate with UEFI memory map handoff. OS drivers register regions and handle hotplug events; missing metadata yields invisible or unsafe memory.
FOLLOW-UP TRAP: Expecting plug-and-play memory without firmware HDM setup.When is Type 3 preferable to Type 2 for a deployment?
diagram
[INT][PCIE-CXL][CXL-PROTOCOLS]
Q: When is Type 3 preferable to Type 2 for a deployment?
A:
Type 3 fits capacity expansion with simpler software when accelerator coherency is unnecessary. Type 2 is for compute devices needing both cache and local memory. Choose based on coherency, latency, and driver maturity—not raw GB alone.
FOLLOW-UP TRAP: Selecting device type by marketing label without workload coherency analysis.Q&A drill guide
diagram
WORKLOAD -> PCIe/CXL SYMPTOM -> TIMING/QUEUE METRIC -> ROOT CAUSE -> FIX -> REGRESSIONSketch while answering
diagram
CXL PROTOCOL LAYERS
CXL.io (enumerate) -> CXL.cache (coherency) -> CXL.mem (capacity)Key takeaways
Always tie controller and PHY counter shifts to application latency and throughput outcomes.
Lock firmware timing profile, thermal condition, and DIMM state before comparing PCIe/CXL captures.
Common pitfalls
Chasing peak bandwidth while ignoring p99 latency and fairness tails.
Changing timing guardbands without separating SI noise from scheduling issues.
Declaring closure without reliability gates, fault injection, and regression replay.