Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutRoadmapCareersInternshipsFAQContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
    • Datatype and Bit Puzzles
      • X-Bit Comparisons and Mixed Arithmetic
      • Signed vs Unsigned Comparison Trap
      • Type Cast Controls Sign Extension
      • Signed Part-Select Is Still Unsigned
      • X Collapse into 2-State `int`
      • Expression Width Drops the Carry
    • Fork Join Puzzles
    • Queue and Array Puzzles
    • String and Casting Puzzles
    • SystemVerilog Language Puzzles: Tricky Q&A
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
Loading lesson

←Datatype and Bit Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SystemVerilog Language Puzzles
  4. Datatype and Bit Puzzles
  5. Expression Width Drops the Carry
On this page

    VLSI DV Interview PuzzlesAll levels

    Expression Width Drops the Carry

    Predict the six output lines. Where does the carry of 200 + 100 survive, and where is it lost?

    Puzzle

    Difficulty: Medium · Puzzle 6 of 6 · Topic: Datatype and Bit Puzzles

    Predict the six output lines. Where does the carry of 200 + 100 survive, and where is it lost?

    Code

    p6.sv
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    module p6;
      bit [7:0] a = 200, b = 100;
      bit [8:0] c;
      initial begin
        $display("t1=%0d", a + b);
        $display("t2=%0d", (a + b) >> 1);
        $display("t3=%0d", {1'b0, a} + b);
        c = a + b;        $display("t4=%0d", c);
        c = (a + b) >> 1; $display("t5=%0d", c);
        $display("t6=%0d", int'(a) + b);
      end
    endmodule

    Hint

    A `$display` argument is self-determined: its width is the widest operand inside it. On the right side of an assignment the width is the maximum of the left-hand side and all operands, and that context also reaches the left operand of a shift.

    Step-by-step solution

    Diagram
    1) In `$display` the expression `a + b` is self-determined at 8 bits, so 300 wraps to 300 - 256 = 44.
    2) `(a + b) >> 1` is still 8 bits: 44 >> 1 = 22.
    3) `{1'b0, a}` is 9 bits, so the add is done in 9 bits and keeps the carry: 300.
    4) `c = a + b`: the assignment context is 9 bits (the width of c), so the add is done in 9 bits: 300.
    5) `c = (a + b) >> 1`: the 9-bit context also applies to the left operand of the shift, so the sum is 300 before shifting and the result is 150, not 22.
    6) `int'(a)` makes the add 32 bits wide: 300.

    Answer

    Answer: t1=44, t2=22, t3=300, t4=300, t5=150, t6=300

    How this was checked

    Checked by running the code in Icarus Verilog 13 and Verilator 5; the printed output supports the answer above. Context width decides whether the carry survives. (Icarus, 4-state) Context width decides whether the carry survives. (Verilator, 2-state)

    Why candidates get it wrong

    The same source text `(a + b) >> 1` gives 22 inside `$display` but 150 when assigned to a 9-bit variable, because width is decided by context, not by the operands alone.

    Interviewer follow-up

    Without declaring a wider variable, how do you make the `t1` expression print 300? Model answer: make one operand wider before the add, for example `a + 9'(b)`, `{1'b0, a} + b` or `a + b + 9'd0`; the add is evaluated at the width of its widest operand, so any wider operand keeps the carry.

    Say it out loud

    I would find the width of the context first, because the width of an add depends on where it is used. Inside the display the add is only 8 bits, so 300 wraps to 44 and the shift gives 22. Assigned to a 9-bit variable, the add is done in 9 bits, so it keeps 300 and the shifted result is 150, and a 9-bit or 32-bit operand also keeps the carry. The trap is that the same source text gives 22 in one place and 150 in another. I would check the widest operand and the destination width every time I see an add.

    Related topics

    • Expression Width & Evaluation Rules

    • Signed & Unsigned Arithmetic

    • Back to Datatype and Bit Puzzles

    • SystemVerilog Language Puzzles section

    Previous

    12 / 293

    Next: Four-Week Route: Week 1

    Up next

    Up nextFour-Week Route: Week 1

    Sign in to save progress

    Practice this lessonPrevious lessonReport an error

    See also

    • X-Bit Comparisons and Mixed Arithmetic
    • Signed vs Unsigned Comparison Trap
    • Type Cast Controls Sign Extension