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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
    • Handle and Copy Puzzles
    • Virtual Method Puzzles
    • Parameterized Class Puzzles
    • Factory Override Puzzles
      • Type Override vs Instance Override Precedence
      • Chained Type Overrides
      • Replace Flag in Repeated set_type_override
      • Overlapping Instance Overrides: First Match Wins
      • Component Override in build_phase
      • Override Timing Relative to create Calls
    • OOP & Testbench Puzzles: Tricky Q&A
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Factory Override Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. OOP & Testbench Puzzles
  4. Factory Override Puzzles
  5. Overlapping Instance Overrides: First Match Wins
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    VLSI DV Interview PuzzlesAll levels

    Overlapping Instance Overrides: First Match Wins

    A wildcard instance override and an exact instance override both match the path of `a0`. Predict the types of `a0` and `a1`.

    Puzzle

    Difficulty: Hard · Puzzle 4 of 6 · Topic: Factory Override Puzzles

    A wildcard instance override and an exact instance override both match the path of `a0`. Predict the types of `a0` and `a1`.

    Code

    design.sv
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    class base_item extends uvm_object;
      `uvm_object_utils(base_item)
      function new(string name="base_item"); super.new(name); endfunction
    endclass
    class dbg_item extends base_item;
      `uvm_object_utils(dbg_item)
      function new(string name="dbg_item"); super.new(name); endfunction
    endclass
    class perf_item extends base_item;
      `uvm_object_utils(perf_item)
      function new(string name="perf_item"); super.new(name); endfunction
    endclass
    
    initial begin
      base_item a0, a1;
      // registered first: wildcard
      base_item::type_id::set_inst_override(
        perf_item::get_type(),
        "uvm_test_top.env.agent*.seqr.*"
      );
      // registered second: exact
      base_item::type_id::set_inst_override(
        dbg_item::get_type(),
        "uvm_test_top.env.agent0.seqr.a0"
      );
      a0 = base_item::type_id::create("a0", null, "uvm_test_top.env.agent0.seqr");
      a1 = base_item::type_id::create("a1", null, "uvm_test_top.env.agent1.seqr");
      $display("a0=%s a1=%s", a0.get_type_name(), a1.get_type_name());
    end

    Hint

    Count how many overrides match `a0`'s full path, then recall how the factory chooses among several matching instance overrides.

    Step-by-step solution

    Diagram
    1) The full path of `a0` is `uvm_test_top.env.agent0.seqr.a0`. It matches both the wildcard (`agent*`, `.*`) and the exact entry. `a1` (`...agent1.seqr.a1`) matches only the wildcard.
    2) UVM does not rank overrides by specificity. Matching instance overrides for a type are checked in registration order and the first match is used.
    3) The wildcard was registered first, so `a0` gets `perf_item`; the exact entry is shadowed and never used.
    4) `a1` gets `perf_item` as well. Result: `a0=perf_item a1=perf_item`.
    5) To make the exact entry win, register it before the wildcard.

    Answer

    Answer: Prints `a0=perf_item a1=perf_item`. There is no specificity ranking: the first registered matching instance override wins, and the wildcard was registered first, shadowing the exact `dbg_item` entry.

    How this was checked

    Checked by running the code in Verilator 5; the printed output supports the answer above. A hand-written model of the documented UVM 1.2 factory rule (not the UVM library): the first matching instance override wins, so registration order decides.

    Why candidates get it wrong

    "Exact beats wildcard" is a common but false mental model carried over from CSS or routing tables. The factory only sees an ordered list, so a broad wildcard registered early quietly hides every later, more specific override.

    Interviewer follow-up

    How would you debug this at runtime using factory print/debug APIs? Model answer: call `uvm_factory::get().print(1)` (or `factory.print()` in a test) to list the instance override table in order, and `factory.debug_create_by_type(base_item::get_type(), "uvm_test_top.env.agent0.seqr", "a0")` to print which override matched for that path; then reorder the registrations or tighten the wildcard.

    Say it out loud

    Both a0 and a1 are perf_item. UVM does not rank overrides by specificity, and the first registered matching instance override wins. The wildcard was registered first, so it shadows the exact entry for a0. The trap is expecting the most specific path to win, and the fix is to register the exact entry before the wildcard.

    Related topics

    • Override Resolution: Who Wins

    • Override Timing, Safety and Debug

    • Back to Factory Override Puzzles

    • OOP & Testbench Puzzles section

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    See also

    • Type Override vs Instance Override Precedence
    • Chained Type Overrides
    • Override Timing Relative to create Calls