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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
    • Handle and Copy Puzzles
    • Virtual Method Puzzles
    • Parameterized Class Puzzles
    • Factory Override Puzzles
      • Type Override vs Instance Override Precedence
      • Chained Type Overrides
      • Replace Flag in Repeated set_type_override
      • Overlapping Instance Overrides: First Match Wins
      • Component Override in build_phase
      • Override Timing Relative to create Calls
    • OOP & Testbench Puzzles: Tricky Q&A
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Factory Override Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. OOP & Testbench Puzzles
  4. Factory Override Puzzles
  5. Replace Flag in Repeated set_type_override
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    VLSI DV Interview PuzzlesAll levels

    Replace Flag in Repeated set_type_override

    Two type overrides are applied for the same base. Predict behavior with `replace=0` and `replace=1`.

    Puzzle

    Difficulty: Medium · Puzzle 3 of 6 · Topic: Factory Override Puzzles

    Two type overrides are applied for the same base. Predict behavior with `replace=0` and `replace=1`.

    Code

    design.sv
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    class base_item extends uvm_object;
      `uvm_object_utils(base_item)
      function new(string name="base_item"); super.new(name); endfunction
    endclass
    class item_a extends base_item;
      `uvm_object_utils(item_a)
      function new(string name="item_a"); super.new(name); endfunction
    endclass
    class item_b extends base_item;
      `uvm_object_utils(item_b)
      function new(string name="item_b"); super.new(name); endfunction
    endclass
    
    initial begin
      base_item::type_id::set_type_override(item_a::get_type(), 0);
      base_item::type_id::set_type_override(item_b::get_type(), 0);
      $display("first=%s", base_item::type_id::create("x").get_type_name());
      base_item::type_id::set_type_override(item_b::get_type(), 1);
      $display("second=%s", base_item::type_id::create("y").get_type_name());
    end

    Hint

    Second call with `replace=0` does not overwrite existing mapping.

    Step-by-step solution

    Diagram
    1) First mapping base->item_a is installed.
    2) Second call with `replace=0` keeps existing mapping unchanged.
    3) `first` therefore prints `item_a`.
    4) Third call with `replace=1` updates mapping to item_b, so `second` prints `item_b`.

    Answer

    Answer: Output is `first=item_a` then `second=item_b`.

    How this was checked

    Checked by running the code in Verilator 5; the printed output supports the answer above. A hand-written model of the documented UVM 1.2 factory rule (not the UVM library): replace=0 keeps the first mapping, replace=1 overwrites it.

    Why candidates get it wrong

    `replace=0` on a second override of the same original type is ignored (UVM warns), so the latest call does not always win; only `replace=1` changes the mapping.

    Interviewer follow-up

    Why can hidden replace defaults create flaky tests across reused env code? Model answer: the default `replace` is 1, so any later `set_type_override` (for example in a reused base test or sequence library) silently replaces your earlier choice, while `replace=0` silently keeps the first one. Which one wins then depends on file and call order, which is why overrides belong in one place (the test) and are checked with `factory.print()`.

    Say it out loud

    First is item_a and second is item_b. The second call with replace set to 0 keeps the existing mapping, so the first print still shows item_a. The later call with replace set to 1 updates the mapping, so the second print shows item_b. The trap is assuming the latest call always wins, so I would check the replace argument.

    Related topics

    • Override Resolution: Who Wins

    • Override Timing, Safety and Debug

    • Back to Factory Override Puzzles

    • OOP & Testbench Puzzles section

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    See also

    • Type Override vs Instance Override Precedence
    • Component Override in build_phase
    • Override Timing Relative to create Calls