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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
    • Covergroup and Coverpoint Puzzles
      • Auto vs explicit bins with illegal transition context
      • Default bin is not scored
      • Bin array math with mixed declarations
      • Transition bin sequence counting
      • illegal_bins vs ignore_bins accounting
      • Same traffic, different denominator
    • Cross Coverage Puzzles
    • Coverage Options Puzzles
    • Coverage Closure and Sampling Timing Puzzles
    • Functional Coverage Puzzles: Tricky Q&A
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Covergroup and Coverpoint Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Functional Coverage Puzzles
  4. Covergroup and Coverpoint Puzzles
  5. Transition bin sequence counting
On this page

    VLSI DV Interview PuzzlesAll levels

    Transition bin sequence counting

    Determine which transition bins hit and give final percentage. Options: none set (all defaults: at_least = 1, weight = 1, auto_bin_max = 64).

    Puzzle

    Difficulty: Medium · Puzzle 4 of 6 · Topic: Covergroup and Coverpoint Puzzles

    Determine which transition bins hit and give final percentage. Options: none set (all defaults: at_least = 1, weight = 1, auto_bin_max = 64).

    Code

    design.sv
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    covergroup cg with function sample(bit [1:0] state);
      cp_state: coverpoint state {
        bins warmup = (0 => 1 => 2);
        bins bounce = (2 => 1 => 2);
        bins reset  = (2 => 0);
      }
    endgroup
    
    initial begin
      cg c = new();
      c.sample(0);
      c.sample(1);
      c.sample(2);
      c.sample(1);
      c.sample(2);
      c.sample(0);
    end

    Hint

    Write the sampled stream first, then slide windows for 3-step and 2-step transitions.

    Step-by-step solution

    Diagram
    1) Sampled stream is 0,1,2,1,2,0.
    2) warmup (0=>1=>2) matches at samples 1..3.
    3) bounce (2=>1=>2) matches at samples 3..5.
    4) reset (2=>0) matches at samples 5..6.
    5) All 3 bins hit -> 3/3 = 100%.

    Answer

    Answer: warmup, bounce, and reset all hit, so coverage is 100% (3/3).

    How this was checked

    Checked by running a model of the rule in a Python model. A model of transition matching over the sampled stream 0,1,2,1,2,0: all three sequences occur, so 3 of 3.

    Why candidates get it wrong

    Candidates often count only non-overlapping windows and miss valid overlapping transition matches.

    Interviewer follow-up

    How many bins remain hit if the last sample c.sample(0) is removed? Model answer: Two: warmup (0=>1=>2) and bounce (2=>1=>2) still match the stream 0,1,2,1,2; reset (2=>0) is lost, so 2/3 = 66.67%.

    Say it out loud

    I would slide a window over the sampled sequence and test every starting position. Warmup, bounce and reset all match, so coverage is 100 percent, three of three. The reason is that transition matches can overlap, because every sample can start a new attempt. The trap is counting only non-overlapping windows and missing a valid match, so I would recheck the sequence by hand.

    Related topics

    • Transition Bins

    • Back to Covergroup and Coverpoint Puzzles

    • Functional Coverage Puzzles section

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    See also

    • Auto vs explicit bins with illegal transition context
    • Default bin is not scored
    • Same traffic, different denominator