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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
    • Covergroup and Coverpoint Puzzles
      • Auto vs explicit bins with illegal transition context
      • Default bin is not scored
      • Bin array math with mixed declarations
      • Transition bin sequence counting
      • illegal_bins vs ignore_bins accounting
      • Same traffic, different denominator
    • Cross Coverage Puzzles
    • Coverage Options Puzzles
    • Coverage Closure and Sampling Timing Puzzles
    • Functional Coverage Puzzles: Tricky Q&A
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Covergroup and Coverpoint Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Functional Coverage Puzzles
  4. Covergroup and Coverpoint Puzzles
  5. Default bin is not scored
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    VLSI DV Interview PuzzlesAll levels

    Default bin is not scored

    How many bins of cp_opcode are scored, and what is its percentage after the four samples? Options: none set (all defaults: at_least = 1, weight = 1, auto_bin_max = 64).

    Puzzle

    Difficulty: Easy · Puzzle 2 of 6 · Topic: Covergroup and Coverpoint Puzzles

    How many bins of cp_opcode are scored, and what is its percentage after the four samples? Options: none set (all defaults: at_least = 1, weight = 1, auto_bin_max = 64).

    Code

    design.sv
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    covergroup cg with function sample(bit [2:0] opcode);
      cp_opcode: coverpoint opcode {
        bins read   = {0};
        bins write  = {1};
        bins atomic = {2,3};
        bins other  = default;
      }
    endgroup
    
    initial begin
      cg c = new();
      c.sample(0);
      c.sample(1);
      c.sample(4);
      c.sample(7);
    end

    Hint

    IEEE 1800 19.5.1: the default bin catches every value no other bin lists, and it is excluded from the coverage calculation.

    Step-by-step solution

    Diagram
    1) Scored bins are read, write and atomic -> 3 bins. other = default catches 4..7 but is not part of the coverage calculation (19.5.1).
    2) Sample 0 hits read, 1 hits write, 4 and 7 land in the default bin (hit, but not scored). atomic (2 or 3) is never hit.
    3) Coverage = 2/3 = 66.67%.

    Answer

    Answer: 3 bins are scored and coverage is 66.67% (read and write hit, atomic missed). The default bin is hit twice but earns no credit.

    How this was checked

    Checked by running a model of the rule in a Python model. A model of the LRM rule: the default bin collects 4 and 7 but is outside the scored bins, leaving 2 of 3.

    Why candidates get it wrong

    Counting other as a fourth bin gives 3/4 = 75% and hides the real hole. The default bin only collects values nobody planned for, so hitting it on 4 and 7 is not progress; atomic is still uncovered.

    Interviewer follow-up

    If you replace bins other = default by the explicit bin bins hi = {[4:7]}, what is the percentage with the same samples? Model answer: hi is an ordinary bin and is scored: 4 bins (read, write, atomic, hi), 3 hit (read, write, hi), so 3/4 = 75%.

    Say it out loud

    I would score only read, write and atomic, so three bins. Read and write are hit, atomic never is, so the answer is two thirds, 66.67 percent. The default bin catches 4 and 7 but is not part of the coverage calculation, so those hits earn nothing. The trap is counting the default bin as a fourth bin and reporting 75 percent; I would next ask how to drive opcode 2 or 3.

    Related topics

    • Auto Bins vs Explicit Bins

    • Bins: Explicit, Auto, Illegal & Ignore

    • Back to Covergroup and Coverpoint Puzzles

    • Functional Coverage Puzzles section

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    Next: Bin array math with mixed declarations

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    See also

    • Transition bin sequence counting
    • illegal_bins vs ignore_bins accounting
    • Same traffic, different denominator