DenseChip

SerDes & High-Speed I/O · All levels

SI/PI Co-Design

Power integrity noise, reference clock quality, EMI/return paths, and thermal/layout constraints for SerDes.

Section goal

Power integrity noise, reference clock quality, EMI/return paths, and thermal/layout constraints for SerDes.

This section trains how to reason from traffic behavior to SerDes mechanism, then close with owner accountability, reliability gates, and release-safe decisions.

How to study this section

  1. Start with each topic hub and draw the mechanism path.

  2. Use reports and debug pages to prove causality before tuning.

  3. Practice worked examples and interview drills with explicit evidence chains.

  4. Close each topic with checklist and silicon impact pages.

Topics

  1. power-integrity-noise/ - Power Integrity and Supply Noise

  2. reference-clock-quality/ - Reference Clock Quality and Distribution

  3. emi-and-return-paths/ - EMI, Return Paths, and Shielding

  4. thermal-and-layout-constraints/ - Thermal, Layout, and Mechanical Constraints

Related topics

SerDes deep dive

Power integrity noise, reference clock quality, EMI/return paths, and thermal/layout constraints for SerDes.

Concept diagram

diagram
SI PI CO DESIGN
power-integrity-noise -> reference-clock-quality -> closure

Metric graph

diagram
MARGIN TREND
healthy ██████
failing ██

Reports and artifacts

  • eye margin log

  • BER/FEC counter sheet

  • coefficient dump

  • JTOL/compliance margin report

Mini case study

A corner board failed link training after package update; isolating lane skew and PI noise restored margin.

Debug branches

  • Classify failure: training, eye, jitter, deskew, or runtime drift

  • Capture coefficient and margin artifacts under fixed thermal tags

  • Correlate SI/PI measurements before retuning adaptation

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this SerDes topic is closed under real traffic?

Practice this lesson