DenseChip

SerDes & High-Speed I/O · All levels

PHY Architecture

Analog front-end, PLL/clock distribution, lane controller FSM, and power-management states in high-speed PHYs.

Section goal

Analog front-end, PLL/clock distribution, lane controller FSM, and power-management states in high-speed PHYs.

This section trains how to reason from traffic behavior to SerDes mechanism, then close with owner accountability, reliability gates, and release-safe decisions.

How to study this section

  1. Start with each topic hub and draw the mechanism path.

  2. Use reports and debug pages to prove causality before tuning.

  3. Practice worked examples and interview drills with explicit evidence chains.

  4. Close each topic with checklist and silicon impact pages.

Topics

  1. analog-front-end/ - Analog Front-End and Slicer/ADC Path

  2. pll-and-clock-distribution/ - PLL and On-Chip Clock Distribution

  3. lane-controller-fsm/ - Lane Controller FSM and Digital Wrapper

  4. power-management-states/ - Power Management and Low-Power States

Related topics

SerDes deep dive

Analog front-end, PLL/clock distribution, lane controller FSM, and power-management states in high-speed PHYs.

Concept diagram

diagram
PHY ARCHITECTURE
analog-front-end -> pll-and-clock-distribution -> closure

Metric graph

diagram
MARGIN TREND
healthy ██████
failing ██

Reports and artifacts

  • eye margin log

  • BER/FEC counter sheet

  • coefficient dump

  • JTOL/compliance margin report

Mini case study

A corner board failed link training after package update; isolating lane skew and PI noise restored margin.

Debug branches

  • Classify failure: training, eye, jitter, deskew, or runtime drift

  • Capture coefficient and margin artifacts under fixed thermal tags

  • Correlate SI/PI measurements before retuning adaptation

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this SerDes topic is closed under real traffic?

Practice this lesson