DenseChip

SerDes & High-Speed I/O · All levels

Clock Data Recovery

CDR loop architecture, phase detectors, jitter tolerance/transfer, lock detect, and holdover behavior.

Section goal

CDR loop architecture, phase detectors, jitter tolerance/transfer, lock detect, and holdover behavior.

This section trains how to reason from traffic behavior to SerDes mechanism, then close with owner accountability, reliability gates, and release-safe decisions.

How to study this section

  1. Start with each topic hub and draw the mechanism path.

  2. Use reports and debug pages to prove causality before tuning.

  3. Practice worked examples and interview drills with explicit evidence chains.

  4. Close each topic with checklist and silicon impact pages.

Topics

  1. cdr-loop-architecture/ - CDR Loop Architecture and Bandwidth

  2. phase-detectors/ - Phase Detectors and Phase Interpolators

  3. jitter-tolerance-transfer/ - Jitter Tolerance and Transfer Functions

  4. lock-detect-and-holdover/ - Lock Detect, Loss of Lock, and Holdover

Related topics

SerDes deep dive

CDR loop architecture, phase detectors, jitter tolerance/transfer, lock detect, and holdover behavior.

Concept diagram

diagram
CLOCK DATA RECOVERY
cdr-loop-architecture -> phase-detectors -> closure

Metric graph

diagram
MARGIN TREND
healthy ██████
failing ██

Reports and artifacts

  • eye margin log

  • BER/FEC counter sheet

  • coefficient dump

  • JTOL/compliance margin report

Mini case study

A corner board failed link training after package update; isolating lane skew and PI noise restored margin.

Debug branches

  • Classify failure: training, eye, jitter, deskew, or runtime drift

  • Capture coefficient and margin artifacts under fixed thermal tags

  • Correlate SI/PI measurements before retuning adaptation

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this SerDes topic is closed under real traffic?

Practice this lesson