Power Integrity and Supply Noise

What this topic teaches

Power Integrity and Supply Noise turns SerDes theory into production-grade review decisions. Fast SerDes switching draws impulse current through package inductance, modulating TX/RX supply and adding jitter and level noise. Decap placement, plane resonance, and regulator bandwidth must be co-designed with PHY floorplan. PI failures mimic channel loss or CDR mis-tuning in lab debug.

The main objective is to identify where the first loss starts in the link service path, prove it with reproducible traces, and close with the smallest owner-controlled fix.

Senior SerDes work is less about isolated register tuning and more about cross-layer causality: traffic shape, command stream legality, bank behavior, PHY margin, and field reliability must agree before signoff.

Senior-engineer framing question

When PSIJ (power-supply induced jitter) and rail ripple (mV) at switching frequency. regresses, can you prove whether the first failure is locality collapse, timing-window pressure, scheduler fairness loss, lane-margin drift, or reliability policy overhead?

SERDES LINK DIAGRAM - Power Integrity and Supply Noise

[Parallel PCS] -> [TX FFE] -> [Channel: package/PCB/cable] -> [RX AFE/CTLE] -> [CDR/Sampler] -> [DFE/DSP] -> [PCS]

Focus: link physical state changes to service-level latency and bandwidth outcomes
Metric tracked: PSIJ (power-supply induced jitter) and rail ripple (mV) at switching frequency.

Architecture and timing visuals

Draw the mechanism before tuning knobs. These visuals are optimized for design reviews, bring-up triage, and interview whiteboards.

SerDes signal path (Power Integrity Noise)

SERDES PATH - Power Integrity Noise

TX PCS -> FFE -> channel -> CTLE -> CDR -> DFE/DSP -> RX PCS
section: si-pi-co-design

Eye and margin lens (Power Integrity Noise)

EYE MARGIN - Power Integrity Noise

width (timing) x height (levels for PAM4)
BER ties to both dimensions + jitter

Power Integrity and Supply Noise diagram

POWER INTEGRITY NOISE - si-pi-co-design

PSIJ (power-supply induced jitter) and rail ripple (mV) at switching frequency.
Key mechanism: Fast SerDes switching draws impulse current through package inductance, modulating TX/RX supply and adding jitter and le...

Array hierarchy context

INSERTION LOSS - Power Integrity and Supply Noise

|SDD21| dB
  0 ----        \____
             \____
                  \_______
                        \________> freq
                         f_Nyquist

Higher loss -> more ISI -> more equalization needed

Command timing context

CDR LOOP - Power Integrity and Supply Noise

data in -> [Phase Detector] -> [Loop Filter] -> [VCO/PI] -> recovered clock
                ^                                    |
                +------------------------------------+

BW trade: tracking vs jitter peaking

Controller queue context

TRAINING FSM - Power Integrity and Supply Noise

Detect -> Electrical Idle -> RX Adapt -> TX FFE -> BER Check -> Align -> Active
   |           |                |           |          |         |
 timeout    partner wait      CTLE/VGA    presets    deskew   mission

Ownership layers

OWNERSHIP LAYERS - Power Integrity and Supply Noise

protocol/MAC     : link firmware owner
PHY digital      : SerDes architect
PHY analog       : PHY analog designer
SI/PI + package  : SI/PI owner
validation       : validation owner

Evidence to collect before changing knobs

Fast closure comes from complete evidence packets, not from isolated counter wins. Every recommendation should carry a metric, artifact, owner, and rollback-safe validation plan.

• Primary metric: PSIJ (power-supply induced jitter) and rail ripple (mV) at switching frequency..

• Primary artifact: PDN impedance plot with measured rail ripple under PRBS load..

• Owners to include: SerDes architect, PHY analog designer, SI/PI owner, validation owner, link firmware owner.

• One reproducible failing traffic slice plus one stable comparator capture.

• One command legality timeline that isolates first failing transition.

• One margin or reliability packet when PHY or RAS behavior is implicated.

Bandwidth-latency operating lens

JITTER BUDGET - Power Integrity and Supply Noise

refclk RJ  + PLL noise + TX RJ/DJ + channel ISI + RX CDR peaking = total TJ
Each block must fit compliance mask and BER target

Root-cause decision tree

SERDES DEBUG TREE - Power Integrity and Supply Noise

symptom: BER / eye / training fail
  |-- training timeout -> presets / partner / FSM
  |-- eye closed -> channel loss / FFE / CTLE
  |-- jitter fail -> CDR BW / refclk / PI noise
  |-- lane specific -> package / via / deskew
  -- runtime drift -> thermal / voltage / EMI

Key takeaways

• Prove first failing transition before touching broad tuning policies.

• Tie command-level behavior to application-visible QoS outcomes.

• Close with accountable owner, rollback criteria, and corner validation.

Common pitfalls

• Optimizing average GB/s while p99 latency and fairness degrade.

• Comparing traces without fixed firmware, timing profile, and thermal tags.

• Declaring closure without reliability and retrain robustness checks.

SerDes deep dive

Power integrity noise, reference clock quality, EMI/return paths, and thermal/layout constraints for SerDes.

Concept diagram

SI PI CO DESIGN
power-integrity-noise -> reference-clock-quality -> closure

Metric graph

MARGIN TREND
healthy ██████
failing ██

Reports and artifacts

• eye margin log

• BER/FEC counter sheet

• coefficient dump

• JTOL/compliance margin report

Mini case study

A corner board failed link training after package update; isolating lane skew and PI noise restored margin.

Debug branches

• Classify failure: training, eye, jitter, deskew, or runtime drift

• Capture coefficient and margin artifacts under fixed thermal tags

• Correlate SI/PI measurements before retuning adaptation

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this SerDes topic is closed under real traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing SerDes captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.