SerDes & High-Speed I/O · All levels
PHY Architecture: Tricky Q&A
Senior interview and review questions for PHY Architecture.
Section Q&A bank
Use these drills after completing all topics in PHY Architecture. Answer with workload context, mechanism proof, artifact, owner, and release decision.
Why does ADC/DSP PAM4 RX demand stricter AFE linearity than NRZ slicer paths?
diagram
[INT][SERDES][PHY-ARCHITECTURE]
Q: Why does ADC/DSP PAM4 RX demand stricter AFE linearity than NRZ slicer paths?
A:
PAM4 decisions depend on resolving four levels simultaneously; compression or clipping collapses level spacing unequally across symbols. NRZ slicer primarily needs threshold crossing timing. INL/DNL and VGA range must cover worst-case channel with margin; nonlinear ISI cannot be fully corrected by digital equalization.
FOLLOW-UP TRAP: Reusing NRZ AFE headroom assumptions for PAM4 without linearity proof.How does PLL phase noise translate to jitter at line rate?
diagram
[INT][SERDES][PHY-ARCHITECTURE]
Q: How does PLL phase noise translate to jitter at line rate?
A:
Phase noise integration over offset frequency bands maps to RJ on the line clock. Spurs at specific offsets appear as deterministic jitter tones in the eye. Reference clock quality, loop bandwidth, and supply isolation dominate. SSC adds intentional low-frequency modulation that CDR must track.
FOLLOW-UP TRAP: Specifying PLL only by lock time without phase noise mask.What digital-analog fencing bug class causes intermittent training failure?
diagram
[INT][SERDES][PHY-ARCHITECTURE]
Q: What digital-analog fencing bug class causes intermittent training failure?
A:
Enabling TX driver or adaptation before analog bias settles, or clearing coefficients while CDR unlocked. Race conditions between firmware register writes and FSM auto-sequences produce nondeterministic outcomes. Assertions on legal analog-digital state pairs catch these in simulation and FPGA bring-up.
FOLLOW-UP TRAP: Blaming channel loss when failure correlates with register write ordering.What must be preserved across L0s entry/exit for link stability?
diagram
[INT][SERDES][PHY-ARCHITECTURE]
Q: What must be preserved across L0s entry/exit for link stability?
A:
Partner negotiation context, minimal adaptation state, and clock recovery continuity per protocol spec. Exiting L0s too slowly hurts latency; too aggressively may skip required re-equalization. Firmware must log whether exit triggered retrain or maintained coefficients.
FOLLOW-UP TRAP: Assuming all low-power exits are transparent without protocol-specific validation.Q&A drill guide
diagram
WORKLOAD -> SerDes SYMPTOM -> TIMING/QUEUE METRIC -> ROOT CAUSE -> FIX -> REGRESSIONSketch while answering
diagram
PHY ARCHITECTURE
analog-front-end -> pll-and-clock-distribution -> closureKey takeaways
Always tie controller and PHY counter shifts to application latency and throughput outcomes.
Lock firmware timing profile, thermal condition, and DIMM state before comparing SerDes captures.
Common pitfalls
Chasing peak bandwidth while ignoring p99 latency and fairness tails.
Changing timing guardbands without separating SI noise from scheduling issues.
Declaring closure without reliability gates, fault injection, and regression replay.