SerDes & High-Speed I/O · All levels
Link Training & Calibration: Tricky Q&A
Senior interview and review questions for Link Training & Calibration.
Section Q&A bank
Use these drills after completing all topics in Link Training & Calibration. Answer with workload context, mechanism proof, artifact, owner, and release decision.
What is the safest order of operations during lane bring-up?
diagram
[INT][SERDES][LINK-TRAINING-CALIBRATION]
Q: What is the safest order of operations during lane bring-up?
A:
Typically: detect partner presence, establish electrical common mode, run receiver detection, apply safe default presets, run adaptation on PRBS, verify BER/FEC, then enable alignment and mission traffic. TX must not launch full swing before partner RX is ready. Each protocol specifies fencing; violating order risks electrical overstress or false lock.
FOLLOW-UP TRAP: Enabling TX output before RX adaptation and detect complete.Why store per-SKU coefficient profiles in firmware?
diagram
[INT][SERDES][LINK-TRAINING-CALIBRATION]
Q: Why store per-SKU coefficient profiles in firmware?
A:
Board and package variation shifts optimal presets; factory calibration reduces training time and improves yield. Field retrain then starts near known-good coefficients, avoiding local minima. Profiles must version with BOM changes and include rollback if new profile fails margin gates.
FOLLOW-UP TRAP: Using one global preset for all board variants to simplify firmware.How does deskew buffer depth affect latency and fault behavior?
diagram
[INT][SERDES][LINK-TRAINING-CALIBRATION]
Q: How does deskew buffer depth affect latency and fault behavior?
A:
Deeper buffers absorb more skew but add fixed latency and gate complexity. Insufficient depth fails on worst-case lane delay spread. Misaligned marker lock with adequate eye per lane still corrupts data—debug must check alignment state, not only per-lane BER.
FOLLOW-UP TRAP: Debugging lane BER while alignment FSM is unlocked or slipping.What runtime signature suggests impending link failure before hard BER collapse?
diagram
[INT][SERDES][LINK-TRAINING-CALIBRATION]
Q: What runtime signature suggests impending link failure before hard BER collapse?
A:
Rising FEC correctable error rate, coefficient wander, shrinking margin on periodic health polls, and increased retrain requests often precede hard failure. Temperature-correlated drift points to SI/PI or thermal margin loss. Trending beats single-threshold BER alarms for fleet ops.
FOLLOW-UP TRAP: Alerting only on uncorrectable errors without monitoring correctable trend.Q&A drill guide
diagram
WORKLOAD -> SerDes SYMPTOM -> TIMING/QUEUE METRIC -> ROOT CAUSE -> FIX -> REGRESSIONSketch while answering
diagram
LINK TRAINING CALIBRATION
lane-bringup-sequence -> coefficient-training -> closureKey takeaways
Always tie controller and PHY counter shifts to application latency and throughput outcomes.
Lock firmware timing profile, thermal condition, and DIMM state before comparing SerDes captures.
Common pitfalls
Chasing peak bandwidth while ignoring p99 latency and fairness tails.
Changing timing guardbands without separating SI noise from scheduling issues.
Declaring closure without reliability gates, fault injection, and regression replay.