Trap Entry/Exit, Interrupt Priority, and Exception Precision: Interview Drills

PROMPT
You observe Worst-case trap-entry cycles, interrupt response jitter, and precise-exception replay success rate under pipeline backpressure. on Trap Entry/Exit, Interrupt Priority, and Exception Precision. Walk through root cause and release decision.

STRONG ANSWER
1. Defines workload and earliest failing mechanism.
2. Explains mechanism: RISC-V unifies interrupts and synchronous exceptions through a trap mechanism that records cause and fault context in mode-specific CSRs before redirecting control to a trap vector. On entry, the core snapshots pc into xepc, encodes reason in xcause, and updates xstatus privilege bits; vectoring behavior depends on xtvec mode and cause class. Correctness requires precise exceptions: younger instructions must not commit when an older fault is taken, even with out-of-order retirement and speculative execution. Systems software then uses xret instructions to restore prior privilege and interrupt-enable state, so implementation bugs in save/restore ordering or delegation filters can produce lost interrupts, nested-trap corruption, or privilege escalation paths.
3. Requests proving artifact: Trap sequencing timeline with CSR writes, pipeline flush points, and nested interrupt masking policy.
4. Proposes bounded fix + owner + rollback-safe validation.

WEAK ANSWER
Suggests generic optimization ideas without mechanism proof or owner accountability.

RISC-V EVIDENCE MATRIX - Trap Entry/Exit, Interrupt Priority, and Exception Precision

+--------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence                 | Tells you                      | Does not prove                 | Next action               |
+--------------------------+--------------------------------+--------------------------------+---------------------------+
| perf counter timeline    | where regression appears       | exact mechanism causality      | correlate with trace      |
| decode/control dump      | control intent per instruction | pipeline side-effect ordering  | inspect retire semantics  |
| trap + CSR logs          | privilege/fault behavior       | performance bottleneck alone   | pair with CPI buckets     |
| MMU/TLB walk trace       | translation behavior           | full system QoS impact         | test mixed workloads      |
| post-fix trend graph     | movement after fix             | long-term stability            | run stress matrix         |
+--------------------------+--------------------------------+--------------------------------+---------------------------+