RISC-V Design · All levels

RVV Vector Basics: Debug Playbook

Debug Playbook for RVV Vector Basics.

Debug playbook

Debug Playbook for RVV Vector Basics is anchored on Sustained vector utilization across mixed-width kernels while keeping scalar fallback correctness intact.. Convert observations into mechanism-backed decisions with explicit ownership.

Freeze workload seed, binary, compiler, firmware, and platform setup.
Find earliest persistent mechanism failure in the timeline.
Build one reduced reproducer for dominant hypothesis.
Patch minimal fix with explicit rollback gate.
Rerun correctness + performance + power matrix.

Decision tree

diagram

ROOT CAUSE TREE - RVV Vector Basics

Sustained vector utilization across mixed-width kernels while keeping scalar fallback correctness intact. regressed
          |
   reproducible on fixed seed?
      /                 \
    no                   yes
    |                     |
env/tool drift       first failing domain?
                     /        |         \
                  decode    execute    memory/MMU
                    |         |            |
               control map  bypass/FU   TLB/walk/perm
                    |
         privilege/CSR side effects checked?

Stop at first confirmed mechanism, then assign explicit owner + fix proof.

Review memo template

diagram

RISC-V REVIEW MEMO - Extensions: Vector & Crypto / RVV Vector Basics

1. Symptom
   - Failing metric: Sustained vector utilization across mixed-width kernels while keeping scalar fallback correctness intact.
   - Failing workload slice: <name>
   - Triggering mode: <privilege/virtualization/interrupt/cache/boot>
   - Build and runtime tags: <toolchain/firmware/RTL revision>

2. Mechanism hypothesis
   - Primary mechanism: RVV decouples architectural vector length from implementation width through vtype and vl, so software scales across cores with different VLEN values. Hardware executes vector instructions over available lanes with tail and mask semantics preserving deterministic behavior when loop trip counts are not multiples of lane width. Correct implementation requires precise exception behavior, clear scalar-vector state transitions, and stable save-restore of vector CSRs across interrupts and context switches.
   - Competing hypotheses: <decode control / hazard / MMU / privilege / integration>
   - Missing evidence: <trace/counter/proof/report>

3. Proposed action
   - Smallest reversible change: <RTL/compiler/runtime/config>
   - Expected movement: <throughput/latency/tail/perf-per-watt>
   - Regression risk: correctness, security, power, timing, software compatibility

4. Signoff
   - Required artifact: Vector bring-up checklist covering vtype/vl programming, tail/mask policy, context-switch state, and scalar fallback tests.
   - Required owners: ISA and compiler lead, vector microarchitecture owner, OS and runtime owner, verification lead
   - Final decision: ship, bounded rollout, rollback, or escalate

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