PCIe/CXL Deep Dive · All levels
Enumeration and Configuration: Tricky Q&A
Senior interview and review questions for Enumeration and Configuration.
Section Q&A bank
Use these drills after completing all topics in Enumeration and Configuration. Answer with workload context, mechanism proof, artifact, owner, and release decision.
Why must BAR sizing happen before enabling memory decode?
diagram
[INT][PCIE-CXL][ENUMERATION-CONFIGURATION]
Q: Why must BAR sizing happen before enabling memory decode?
A:
Sizing writes all-ones to BARs to discover required aperture size without decoding conflicts. Enabling decode before sizing can cause MMIO aliases, DMA to wrong regions, or firmware hangs when overlapping assignments exist.
FOLLOW-UP TRAP: Programming command register memory enable before BAR sizing completes.What breaks when bridge subordinate bus numbers are programmed incorrectly?
diagram
[INT][PCIE-CXL][ENUMERATION-CONFIGURATION]
Q: What breaks when bridge subordinate bus numbers are programmed incorrectly?
A:
Config cycles may reach the wrong downstream device or never reach a subtree. TLP routing uses bus numbers in headers; inconsistent bridge programming causes silent config read failures or devices appearing on phantom buses.
FOLLOW-UP TRAP: Fixing only endpoint config without validating upstream bridge bus registers.How do extended capabilities differ from legacy capability lists in debug?
diagram
[INT][PCIE-CXL][ENUMERATION-CONFIGURATION]
Q: How do extended capabilities differ from legacy capability lists in debug?
A:
Extended capabilities use a 32-bit header chain with different alignment and versioning rules. Walk logic must handle ECRC-capable devices, vendor-specific blocks, and CXL DVSEC entries without stopping at the first unknown ID.
FOLLOW-UP TRAP: Using legacy-only parsers on PCIe 4.0/5.0 devices with deep extended chains.Why can OS re-enumeration break a CXL memory device?
diagram
[INT][PCIE-CXL][ENUMERATION-CONFIGURATION]
Q: Why can OS re-enumeration break a CXL memory device?
A:
CXL.mem registration depends on HDM decode setup and host-managed region metadata established during firmware handoff. If the OS reallocates MMIO or resets HDM without preserving coherence metadata, memory expansion windows become inaccessible or incoherent.
FOLLOW-UP TRAP: Assuming standard PCI hotplug semantics apply unchanged to CXL memory devices.Q&A drill guide
diagram
WORKLOAD -> PCIe/CXL SYMPTOM -> TIMING/QUEUE METRIC -> ROOT CAUSE -> FIX -> REGRESSIONSketch while answering
diagram
ENUMERATION PATH
probe VID/DID -> size BARs -> assign bus numbers -> enable features -> driver bindKey takeaways
Always tie controller and PHY counter shifts to application latency and throughput outcomes.
Lock firmware timing profile, thermal condition, and DIMM state before comparing PCIe/CXL captures.
Common pitfalls
Chasing peak bandwidth while ignoring p99 latency and fairness tails.
Changing timing guardbands without separating SI noise from scheduling issues.
Declaring closure without reliability gates, fault injection, and regression replay.