PCIe/CXL Deep Dive · All levels
Debug, Compliance, and Performance: Tricky Q&A
Senior interview and review questions for Debug, Compliance, and Performance.
Section Q&A bank
Use these drills after completing all topics in Debug, Compliance, and Performance. Answer with workload context, mechanism proof, artifact, owner, and release decision.
What makes a protocol analyzer capture actionable versus overwhelming?
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[INT][PCIE-CXL][DEBUG-COMPLIANCE]
Q: What makes a protocol analyzer capture actionable versus overwhelming?
A:
Actionable captures have precise triggers on error events, include pre/post windows, and correlate with register snapshots. Raw multi-hour traces without filters delay triage and miss first-failure transitions.
FOLLOW-UP TRAP: Collecting full-speed traces without error-qualified triggers.How do you distinguish retimer issues from endpoint PHY issues in LTSSM debug?
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[INT][PCIE-CXL][DEBUG-COMPLIANCE]
Q: How do you distinguish retimer issues from endpoint PHY issues in LTSSM debug?
A:
Retimer problems often appear at segment boundaries with repeated recovery on specific lanes; endpoint issues persist across retimer bypass tests. A/B topology experiments and retimer FW logs isolate the segment.
FOLLOW-UP TRAP: Replacing endpoint cards without testing retimer firmware or cable plant.What belongs in a compliance regression gate versus one-time signoff?
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[INT][PCIE-CXL][DEBUG-COMPLIANCE]
Q: What belongs in a compliance regression gate versus one-time signoff?
A:
Electrical and protocol regressions for speed changes, EQ updates, and firmware releases belong in CI-like gates. One-time structural tests may sign off architecture, but any change to PHY/FW needs targeted replay.
FOLLOW-UP TRAP: Treating initial compliance pass as permanent without change-triggered replay.Why can increasing MPS hurt real workload performance?
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[INT][PCIE-CXL][DEBUG-COMPLIANCE]
Q: Why can increasing MPS hurt real workload performance?
A:
Larger payloads improve peak bandwidth but increase completion splitting complexity, buffer pressure, and latency for small transactions. Mixed workloads may regress when MPS favors bulk DMA over latency-sensitive traffic.
FOLLOW-UP TRAP: Maximizing MPS because benchmark tools report higher GB/s only.Q&A drill guide
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WORKLOAD -> PCIe/CXL SYMPTOM -> TIMING/QUEUE METRIC -> ROOT CAUSE -> FIX -> REGRESSIONSketch while answering
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DEBUG CLOSURE LOOP
trigger capture -> hypothesis -> bounded fix -> compliance/perf replayKey takeaways
Always tie controller and PHY counter shifts to application latency and throughput outcomes.
Lock firmware timing profile, thermal condition, and DIMM state before comparing PCIe/CXL captures.
Common pitfalls
Chasing peak bandwidth while ignoring p99 latency and fairness tails.
Changing timing guardbands without separating SI noise from scheduling issues.
Declaring closure without reliability gates, fault injection, and regression replay.