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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
    • Classic Brain Teasers
    • Probability Puzzles
    • Digital Logic Puzzles
    • Debugging Riddles
      • Race-Region Printout: What Does Each Monitor Print?
      • Reset Release Leaves the FSM in an Illegal State
      • always_comb with NBA and Missing Else
      • UVM Analysis Port Handle Reuse
      • join_any Timeout Ghost Thread
      • Randomization Always Fails: Hidden Unsat
    • Logic & Aptitude Puzzles: Tricky Q&A
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Debugging Riddles
  1. Topics
  2. DV Interview Puzzles
  3. Logic & Aptitude Puzzles
  4. Debugging Riddles
  5. Randomization Always Fails: Hidden Unsat
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    VLSI DV Interview PuzzlesAll levels

    Randomization Always Fails: Hidden Unsat

    A constraint block fails every randomize call. Find the logical contradiction.

    Puzzle

    Difficulty: Easy · Puzzle 6 of 6 · Topic: Debugging Riddles

    A constraint block fails every randomize call. Find the logical contradiction.

    Code

    design.sv
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    class pkt;
      rand bit [3:0] addr;
      constraint c {
        addr inside {[0:15]};
        addr[0] == 1'b1;   // odd
        addr % 4 == 0;     // multiple of 4
      }
    endclass

    Hint

    Check parity implied by modulo condition.

    Step-by-step solution

    Diagram
    1) addr % 4 == 0 means addr is divisible by 4, so its two low bits are 00 and addr[0] is 0.
    2) The other constraint requires addr[0] == 1.
    3) These cannot both hold, so the solver has no legal solution and randomize() returns 0 (Verilator reports UNSATCONSTR).
    4) Fix by deciding the intent: for odd addresses drop the %4 constraint; for 4-aligned addresses drop addr[0]==1; for the odd stride-4 set {1,5,9,13} use addr % 4 == 1.

    Answer

    Answer: Constraint set is unsatisfiable: odd-number requirement conflicts with multiple-of-4 requirement.

    How this was checked

    Checked by running the code in Verilator 5; the printed output supports the answer above. Verilator 5.048: the original constraints are unsatisfiable (every randomize() returns 0); addr % 4 == 1 works and only produces 1, 5, 9, 13.

    Why candidates get it wrong

    Changing seeds or solver options before checking the constraints by hand; two constraints on the same low bits (odd vs multiple of 4) can never both hold.

    Interviewer follow-up

    How would you encode legal addresses as a weighted distribution instead? Model answer: constraint c { addr dist { 4'h0 := 4, [4'h4:4'h8] :/ 8, 4'hC := 1 }; } Here := gives each value in a range the stated weight and :/ divides the stated weight over the range, so 4,5,6,7,8 get 8/5 each. Weights are relative, not percentages.

    Say it out loud

    I'll check the constraints by hand before touching seeds. A multiple of four has its two low bits at zero, so address bit zero is zero. The other constraint requires address bit zero to be one. Those cannot both hold, so the solver has no solution and randomize returns zero. The fix is to decide the intent: drop one constraint, or use address mod four equals one for odd stride-four addresses. The trap is changing seeds or solver options before looking at the constraints.

    Related topics

    • Testing Hypotheses and Minimal Repros

    • Back to Debugging Riddles

    • Logic & Aptitude Puzzles section

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    See also

    • Race-Region Printout: What Does Each Monitor Print?
    • Reset Release Leaves the FSM in an Illegal State
    • always_comb with NBA and Missing Else