Delay Models and Slack · synthesis

Part 3 of 9Constraints and TimingIntermediate

5topics
5lessons

Synthesis scores every timing path with two numbers: when the signal arrives and when it is required. Their difference is the slack, and the path with the worst slack is the critical path. This topic hangs all five lessons on one running example so the numbers stay comparable across pages.

The example is a small block called vipexp: a launching flop, four combinational stages (NAND2, then NOR2, then XOR2, then XNOR2), and a capturing flop, with one tap output per stage. The taps exist for one honest reason: without them ABC would merge the chain into fewer cells, and the four-stage path the lessons price would disappear. Every lesson maps the same RTL against the teaching library course.lib with the same output load, so a number learnt on one page still holds on the next.

Term	Meaning
Arrival time	When the signal actually reaches a point, adding clock-to-Q, cell and net delays along the path.
Required time	When the signal must reach a point, set by the capturing clock edge minus margins.
Slack	Required minus arrival. Positive means margin; negative means the path fails.
Critical path	The path with the worst (smallest) slack. It sets the maximum speed of the block.
Cell delay	Delay through a gate, read from the library delay tables for the stage slew and load.
Net delay	Delay along a wire, estimated at synthesis time and known only after layout.

How arrival, required time, slack and the critical path relate.

Arrival and required time give slack; the worst slack names the critical path.

Lesson	What it covers
Arrival, Required Time and Slack	Arrival, required and slack on the shared path, with the recorded ABC delay.
Setup, Hold and Clock-to-Q	Launch and capture edges, setup and hold checks, and a worked pair.
Cell Delay Models	Table versus linear cell models at the same loads, with the fit error charted.
Wire Delay at Synthesis Time	The same path under two output loads, and what a wire estimate hides.
A Static Timing Calculator	A runnable Python calculator over the recorded path, checked against ABC.

Check yourself Arrival is 0.78 ns and required time is 0.94 ns. What is the slack, and does the path meet timing?

Slack is 0.94 minus 0.78, which is plus 0.16 ns. Positive slack means the path meets timing with margin to spare.

How this was checked

The hub runs nothing; its diagram sketches the lesson structure. The evidence for each claim sits on the five lesson pages, each recorded with Yosys and ABC through the course checker (scripts/tools/run-rtl-testbenches.mjs with COURSE=synth).

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Term

Meaning

Arrival time

When the signal actually reaches a point, adding clock-to-Q, cell and net delays along the path.

Required time

When the signal must reach a point, set by the capturing clock edge minus margins.

Slack

Required minus arrival. Positive means margin; negative means the path fails.

Critical path

The path with the worst (smallest) slack. It sets the maximum speed of the block.

Cell delay

Delay through a gate, read from the library delay tables for the stage slew and load.

Net delay

Delay along a wire, estimated at synthesis time and known only after layout.

Lesson

What it covers

Arrival, Required Time and Slack

Arrival, required and slack on the shared path, with the recorded ABC delay.

Setup, Hold and Clock-to-Q

Launch and capture edges, setup and hold checks, and a worked pair.

Cell Delay Models

Table versus linear cell models at the same loads, with the fit error charted.

Wire Delay at Synthesis Time

The same path under two output loads, and what a wire estimate hides.

A Static Timing Calculator

A runnable Python calculator over the recorded path, checked against ABC.