BERT, Eye Scan, and Error Analysis

What this topic teaches

BERT, Eye Scan, and Error Analysis turns SerDes theory into production-grade review decisions. BERTs stress links with PRBS or compliance patterns while error counters and eye scanners map margin. Eye scan sweeps phase and voltage to build two-dimensional bathtub curves. Correlating BER floors with FEC correctables distinguishes analog margin from protocol issues.

The main objective is to identify where the first loss starts in the link service path, prove it with reproducible traces, and close with the smallest owner-controlled fix.

Senior SerDes work is less about isolated register tuning and more about cross-layer causality: traffic shape, command stream legality, bank behavior, PHY margin, and field reliability must agree before signoff.

Senior-engineer framing question

When BER at target confidence and eye width/height at 1e-12 or protocol threshold. regresses, can you prove whether the first failure is locality collapse, timing-window pressure, scheduler fairness loss, lane-margin drift, or reliability policy overhead?

SERDES LINK DIAGRAM - BERT, Eye Scan, and Error Analysis

[Parallel PCS] -> [TX FFE] -> [Channel: package/PCB/cable] -> [RX AFE/CTLE] -> [CDR/Sampler] -> [DFE/DSP] -> [PCS]

Focus: link physical state changes to service-level latency and bandwidth outcomes
Metric tracked: BER at target confidence and eye width/height at 1e-12 or protocol threshold.

Architecture and timing visuals

Draw the mechanism before tuning knobs. These visuals are optimized for design reviews, bring-up triage, and interview whiteboards.

SerDes signal path (Bert And Eye Scan)

SERDES PATH - Bert And Eye Scan

TX PCS -> FFE -> channel -> CTLE -> CDR -> DFE/DSP -> RX PCS
section: validation-debug

Eye and margin lens (Bert And Eye Scan)

EYE MARGIN - Bert And Eye Scan

width (timing) x height (levels for PAM4)
BER ties to both dimensions + jitter

BERT, Eye Scan, and Error Analysis diagram

BERT AND EYE SCAN - validation-debug

BER at target confidence and eye width/height at 1e-12 or protocol threshold.
Key mechanism: BERTs stress links with PRBS or compliance patterns while error counters and eye scanners map margin. Eye scan sweeps ph...

Array hierarchy context

INSERTION LOSS - BERT, Eye Scan, and Error Analysis

|SDD21| dB
  0 ----        \____
             \____
                  \_______
                        \________> freq
                         f_Nyquist

Higher loss -> more ISI -> more equalization needed

Command timing context

CDR LOOP - BERT, Eye Scan, and Error Analysis

data in -> [Phase Detector] -> [Loop Filter] -> [VCO/PI] -> recovered clock
                ^                                    |
                +------------------------------------+

BW trade: tracking vs jitter peaking

Controller queue context

TRAINING FSM - BERT, Eye Scan, and Error Analysis

Detect -> Electrical Idle -> RX Adapt -> TX FFE -> BER Check -> Align -> Active
   |           |                |           |          |         |
 timeout    partner wait      CTLE/VGA    presets    deskew   mission

Ownership layers

OWNERSHIP LAYERS - BERT, Eye Scan, and Error Analysis

protocol/MAC     : link firmware owner
PHY digital      : SerDes architect
PHY analog       : PHY analog designer
SI/PI + package  : SI/PI owner
validation       : validation owner

Evidence to collect before changing knobs

Fast closure comes from complete evidence packets, not from isolated counter wins. Every recommendation should carry a metric, artifact, owner, and rollback-safe validation plan.

• Primary metric: BER at target confidence and eye width/height at 1e-12 or protocol threshold..

• Primary artifact: Bathtub curve and eye heatmap with BER confidence interval..

• Owners to include: SerDes architect, PHY analog designer, SI/PI owner, validation owner, link firmware owner.

• One reproducible failing traffic slice plus one stable comparator capture.

• One command legality timeline that isolates first failing transition.

• One margin or reliability packet when PHY or RAS behavior is implicated.

Bandwidth-latency operating lens

JITTER BUDGET - BERT, Eye Scan, and Error Analysis

refclk RJ  + PLL noise + TX RJ/DJ + channel ISI + RX CDR peaking = total TJ
Each block must fit compliance mask and BER target

Root-cause decision tree

SERDES DEBUG TREE - BERT, Eye Scan, and Error Analysis

symptom: BER / eye / training fail
  |-- training timeout -> presets / partner / FSM
  |-- eye closed -> channel loss / FFE / CTLE
  |-- jitter fail -> CDR BW / refclk / PI noise
  |-- lane specific -> package / via / deskew
  -- runtime drift -> thermal / voltage / EMI

Key takeaways

• Prove first failing transition before touching broad tuning policies.

• Tie command-level behavior to application-visible QoS outcomes.

• Close with accountable owner, rollback criteria, and corner validation.

Common pitfalls

• Optimizing average GB/s while p99 latency and fairness degrade.

• Comparing traces without fixed firmware, timing profile, and thermal tags.

• Declaring closure without reliability and retrain robustness checks.

SerDes deep dive

Compliance fixtures, BERT/eye scan, failure signature debug, and production screening for SerDes signoff.

Concept diagram

VALIDATION DEBUG
compliance-test-fixtures -> bert-and-eye-scan -> closure

Metric graph

MARGIN TREND
healthy ██████
failing ██

Reports and artifacts

• eye margin log

• BER/FEC counter sheet

• coefficient dump

• JTOL/compliance margin report

Mini case study

A corner board failed link training after package update; isolating lane skew and PI noise restored margin.

Debug branches

• Classify failure: training, eye, jitter, deskew, or runtime drift

• Capture coefficient and margin artifacts under fixed thermal tags

• Correlate SI/PI measurements before retuning adaptation

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this SerDes topic is closed under real traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing SerDes captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.