SerDes & High-Speed I/O · All levels
SerDes Foundations & Signaling: Tricky Q&A
Senior interview and review questions for SerDes Foundations & Signaling.
Section Q&A bank
Use these drills after completing all topics in SerDes Foundations & Signaling. Answer with workload context, mechanism proof, artifact, owner, and release decision.
Why does PAM4 reduce symbol rate but often increase receiver complexity versus NRZ?
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[INT][SERDES][SERDES-FOUNDATIONS]
Q: Why does PAM4 reduce symbol rate but often increase receiver complexity versus NRZ?
A:
PAM4 sends two bits per UI by using four amplitude levels, so the Nyquist bandwidth per Gbps is lower. However, vertical eye height shrinks roughly by a factor related to level spacing, requiring linear equalization, ADC/DSP, and tighter level tracking. Noise, compression, and ISI affect level separation directly, so margin analysis must include SNR and level wander—not just timing eye width.
FOLLOW-UP TRAP: Assuming PAM4 is always easier because the UI is longer in time.What is the first architectural check when serializer FIFO over/under-runs appear?
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[INT][SERDES][SERDES-FOUNDATIONS]
Q: What is the first architectural check when serializer FIFO over/under-runs appear?
A:
Verify clock domain relationship between parallel-side clock and multiplied serial clock, including ppm offset and spread-spectrum interaction. FIFO depth must cover worst-case skew plus SSC modulation. Check gearbox ratio, backpressure from PCS, and whether lane bonding alignment stalls one lane. Only after clock/FIFO contract is proven should equalization or channel loss be blamed.
FOLLOW-UP TRAP: Jumping to channel equalization before proving parallel-to-serial clock integrity.How do retimers change link-training and debug assumptions?
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[INT][SERDES][SERDES-FOUNDATIONS]
Q: How do retimers change link-training and debug assumptions?
A:
Retimers slice the channel into segments, each with independent adaptation and clock recovery. Training may occur per segment; failures can localize to pre- or post-retimer paths. Latency and protocol handling (transparent vs redriver vs full retimer) affect compliance and error isolation. Debug must capture per-segment eye and coefficient state, not only endpoint PHY registers.
FOLLOW-UP TRAP: Treating a retimed link as a single analog channel for margin analysis.Which jitter components typically dominate at 56G+ PAM4 and why?
diagram
[INT][SERDES][SERDES-FOUNDATIONS]
Q: Which jitter components typically dominate at 56G+ PAM4 and why?
A:
At high rates, DJ from ISI and bounded interference often dominates eye closure alongside RJ from PLL and supply noise. Reference clock quality sets a floor, but TX/RX supply ripple and crosstalk convert to timing and level errors. PAM4 adds level-spacing jitter sensitivity. Budgeting must separate timing jitter from amplitude noise effects on level decisions.
FOLLOW-UP TRAP: Reporting only RMS jitter without separating RJ/DJ and level-noise terms.Q&A drill guide
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WORKLOAD -> SerDes SYMPTOM -> TIMING/QUEUE METRIC -> ROOT CAUSE -> FIX -> REGRESSIONSketch while answering
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SERDES FOUNDATIONS
serializer-deserializer-basics -> nrz-pam4-signaling -> closureKey takeaways
Always tie controller and PHY counter shifts to application latency and throughput outcomes.
Lock firmware timing profile, thermal condition, and DIMM state before comparing SerDes captures.
Common pitfalls
Chasing peak bandwidth while ignoring p99 latency and fairness tails.
Changing timing guardbands without separating SI noise from scheduling issues.
Declaring closure without reliability gates, fault injection, and regression replay.