Scenario: Equalization Training Limit Cycle

Scenario

Link training logs show TX FFE and RX CTLE coefficients oscillating between two presets without BER improvement. Bring-up succeeds on golden boards but fails on 15% of production boards at the same data rate.

OBSERVED METRIC
Training iteration count exceeds timeout with coefficient toggling and flat BER.

45-MINUTE INTERVIEW FLOW
0-5: scope traffic and SLA context
5-15: map first failing SerDes transition
15-25: identify proving artifacts
25-35: propose bounded fix with owner
35-45: state validation matrix and rollback

Common pitfalls

• Increasing adaptation step size without hysteresis or staged training order.

• Using one global preset table across board variants with different channel loss.

• Declaring PASS on brief BER windows while coefficients remain unstable.

Scenario debrief

Score candidate response on traffic framing, timing proof, mitigation boundedness, and regression discipline.

request stream -> controller policy -> SerDes timing behavior -> measured outcome

latency/bandwidth trend

Debrief prompts

1. Which SerDes timing or queue behavior fails first in evidence?

2. Which smallest safe controller, PHY, or policy change addresses it?

3. Which benchmark + counter gate proves closure under production traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing SerDes captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.