SerDes & High-Speed I/O · All levels

S-Parameters, TDR, and Eye Diagrams: Review Checklist

Review Checklist for S-Parameters, TDR, and Eye Diagrams.

Review checklist

Review Checklist for S-Parameters, TDR, and Eye Diagrams focuses on SDD21/SDD11 quality and measured eye width/height at target BER.. The purpose is to turn link observations into mechanism-backed actions with explicit owners and release-safe validation.

  • Workload scope and SLA targets are explicit.

  • Environment tags are locked and reproducible.

  • First failing transition is proven by command-level evidence.

  • Owner and rollback criteria are documented.

  • Validation matrix covers performance, stability, and reliability.

  • Owners signed: SerDes architect, PHY analog designer, SI/PI owner, validation owner, link firmware owner.

SerDes deep dive

Loss budgets, S-parameters, eye diagrams, crosstalk, reflections, and package/board/via effects that define the physical channel.

Concept diagram

diagram
CHANNEL SIGNAL INTEGRITY
channel-loss-budget -> s-parameters-and-eye-diagrams -> closure

Metric graph

diagram
MARGIN TREND
healthy ██████
failing ██

Reports and artifacts

  • eye margin log

  • BER/FEC counter sheet

  • coefficient dump

  • JTOL/compliance margin report

Mini case study

A corner board failed link training after package update; isolating lane skew and PI noise restored margin.

Debug branches

  • Classify failure: training, eye, jitter, deskew, or runtime drift

  • Capture coefficient and margin artifacts under fixed thermal tags

  • Correlate SI/PI measurements before retuning adaptation

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this SerDes topic is closed under real traffic?

Key takeaways

  • Always tie controller and PHY counter shifts to application latency and throughput outcomes.

  • Lock firmware timing profile, thermal condition, and DIMM state before comparing SerDes captures.

Common pitfalls

  • Chasing peak bandwidth while ignoring p99 latency and fairness tails.

  • Changing timing guardbands without separating SI noise from scheduling issues.

  • Declaring closure without reliability gates, fault injection, and regression replay.

Review checklist explanation

A checklist here protects against false closure. Every item should map to a known link failure mode.

For S-Parameters, TDR, and Eye Diagrams, minimum checklist: workload scope, SDD21/SDD11 quality and measured eye width/height at target BER., artifact evidence (De-embedded SDD21 plot with simulated vs measured eye at compliance point.), bottleneck class, owner, rollback path, and corner-matrix validation.

If controller or firmware changed, include fairness and RAS checks. If PHY or package assumptions changed, include SI/PI and thermal guardband evidence.