Same chip, different speeds

Two transistors millimetres apart do not switch at the same speed. On-chip variation (OCV) models this with derating factors.

For a setup check, the launch clock and data paths are made slower (late derate, for example ×1.08) and the capture clock path faster (early derate, for example ×0.92). Hold reverses the early/late assignments.

The same path, now derated

The derate turns a passing path into a failing one. Before common-path correction, independent early/late assignments also introduce pessimism on the shared clock segment. The constructed tree below gives a 0.08 ns correction for this pessimism.

For static common-path variation, the shared physical clock buffers and wires cannot be both slow for launch and fast for capture in the same analysis. This does not imply identical delay on successive clock edges: temporal jitter and other time-dependent effects need separate treatment.

Common-path pessimism removal (CRPR / CPPR)

Follow the tree from the source to the split. Both checks contain the same physical trunk, but the independent worst-case setup calculation counts it late on launch and early on capture. For this simple static flat-derate model, that creates 0.08 ns of artificial relative-clock penalty. The two branches after the split are different physical paths, so their early/late difference is not canceled.

Common clock path delay (shared trunk):   0.50 ns
CRPR = 0.50 x (1.08 - 0.92) = 0.08 ns
Slack after pessimism removal = -0.148 + 0.08 = -0.068 ns

The result is still negative. A design that looks fine without derates can fail with them, and the gap is real margin the chip needs.

Rebuild the setup slack from the branches

This reproduces the rounded -0.068 ns result above. Setup time and uncertainty were held fixed for this teaching example; a signoff flow uses the library checks and variation settings appropriate to its analysis view.

Hold reverses early and late, not the benefit of removal

For a constructed flat-OCV hold example using the same clock tree and derates, take nominal clk-to-Q=0.30 ns and minimum logic=0.10 ns, with hold=0.06 ns and hold uncertainty=0.05 ns held fixed. Hold uses an early launch/data path and a late capture path. It still adds the removable shared-clock pessimism to slack.

Depth-dependent and statistical derating

A flat derate punishes deep paths most. Depth-aware and statistical methods remove some of that pessimism.

An illustrative AOCV late-derate table (the numbers are made up to show the shape):

Common mistakes

Related topics

• Timing exceptions