One clock input drives every flop on the chip. A single driver cannot carry that load with a clean, even edge.
Clock tree synthesis (CTS) builds a buffer tree instead. Every flop then sees the edge at nearly the same time with a clean slope.
Read the tree from the source down. Every flop group sees the same edge, but each branch delays it by a different amount.
Load: the left buffer drives 40 flops and the middle one drives 10. More load means a slower transition, so the left group sees its edge later.
Depth: the right branch passes through a clock gate and then a buffer, one level more than the other two branches, so its edge is later again.
The trunk is shared: delay above the split reaches every flop equally and adds no skew. Skew comes only from the branches below it.
Source of skew | Cause | What helps |
|---|---|---|
Unequal buffer depth | Branches with different numbers of levels | CTS balances depth and delay |
Unequal loads | A buffer driving 40 flops versus 10 | Cluster sinks, size buffers |
Wire RC | Long routes have different delay | Place related flops together; shield and route clocks first |
Clock gating cells | The gate is an extra cell on some branches | Balance the tree through the gates |
Different clocks derived from one source | Dividers, muxes | Treat as separate clocks with explicit constraints |
Variation | Process and voltage differences along the tree | OCV derates and margin (see below) |
Crosstalk | Neighbouring signals couple into clock wires | Spacing and shielding for clock nets |
Skew: the spread of arrival times across all sinks (target tens of picoseconds).
Insertion delay: the time from the clock source to the sinks.
Transition time at the sinks, so flops see crisp edges.
Power: the clock network is often 20 to 40 % of dynamic power; fewer, smaller buffers help.
RTL designers shape the clock tree through sink count, clock-gate placement, and clock count. A design with fifteen derived clocks is a hard clock tree problem even when every module is small.
The divider output needs approved clock distribution and a divide-by-4 generated clock, including phase/startup assumptions. Time related-clock crossings and review CDC/reset behavior as appropriate; do not declare them asynchronous merely because the rates differ. A main-clock enable can simplify clock relationships but needs enable timing/fanout and power review.