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Course contents

  • How to Use This Course
  • Reading Paths
  • Glossary
  • Metrics Reference
  • Formal Cheat Sheet
  • Formal Foundations19
  • Properties and SVA16
  • Property Development and Constraints19
  • Proof Engines and Convergence23
  • Formal Applications20
  • Equivalence Checking14
    • Combinational Equivalence and the Miter
    • Sequential Equivalence
      • Product Machine and State Correspondence
      • pipe3 and Its Retimed Twin
      • Latency Alignment and Reset
      • FSM Recoding and Clock-Gating Equivalence
    • RTL to Gate: What LEC Assumes
    • ECO and Alternative-Implementation Checks
  • Formal Coverage and Signoff15
  • Methodology and Debug13
  • Interview Prep15
  • Capstone: A Chip-Block Verification Lab24
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←Equivalence Checking
  1. Topics
  2. Formal Verification
  3. Equivalence Checking
  4. Sequential Equivalence

Part 6 of 10Part 6 of 10/Equivalence CheckingAll levels

Sequential Equivalence

Two sequential machines, one shared stimulus, one invariant relating their states: the product machine.

  • 4topics
  • 4lessons

Retiming moves a register across a multiplier and the netlist still matches the RTL cycle by cycle at the outputs, while nothing matches in the middle. A one-to-one comparison of registers fails everywhere, correctly, because the states genuinely differ. Sequential equivalence compares the machines from reset on the same inputs and asserts equal outputs, with an invariant that relates the two state spaces where they legitimately diverge.

Lesson

After it you can...

Product Machine and State Correspondence

Build a product machine and write the correspondence invariant its induction needs.

pipe3 and Its Retimed Twin

Prove a retimed pipeline equivalent and read the mismatch of a dropped operand bit.

Latency Alignment and Reset

Align latencies honestly and compare only after a defined point.

FSM Recoding and Clock-Gating Equivalence

Prove recoding and gating with map invariants, and name what needs sequential methods.

Suggested order: top to bottom. The product machine is the shared idea; the retimed pipeline is its main workout; alignment and reset are the two traps inside every sequential comparison; recoding and gating close with the transformations that break one-to-one matching. The induction behind the product machine is taught at k-induction.

Two conditions hold for every proof in this topic. First, the equivalence is from reset: the first step of every miter is held in reset, so both machines start from their reset states and the proof says nothing about arbitrary power-up contents. Second, the model is two-state: a register that is not reset is an arbitrary 0 or 1, never an unknown, so a two-state equivalence cannot show a difference in X-pessimism or X-optimism between two descriptions. Whether state after reset is independent of power-up values is a reset-determinism question, answered by its own proof and not by the miter.

Both designs leave reset together and step on identical inputs; outputs are compared each cycle, passing on agreement and returning a counterexample to induction that demands a state-correspondence invariant.
A product machine: reset both designs, step them on shared inputs, check outputs, and strengthen with a state map when induction fails.
Check yourself Why does sequential equivalence need an invariant when combinational equivalence does not?

Combinational blocks have no state: one input vector decides the answer. Sequential machines carry history, so the induction step starts from arbitrary state pairs, including pairs no shared stimulus can reach. The invariant excludes those pairs.

If asked why a retimed netlist fails one-to-one comparison yet is correct, answer with the product machine: states differ by construction, outputs agree after alignment, and the proof relates the two state spaces instead of matching registers by name.

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See also

  • Combinational Equivalence and the Miter
  • RTL to Gate: What LEC Assumes
  • ECO and Alternative-Implementation Checks