DenseChip

Formal Verification · All levels

Equivalence Checking (LEC/SEC)

Practical equivalence checking for formal signoff: combinational key-point mapping, sequential equivalence under pipeline and latency shifts, post-synthesis RTL-to-gate closure, and robust debug strategy for ECO, retiming, and clock-gating transformations.

Section goal

Practical equivalence checking for formal signoff: combinational key-point mapping, sequential equivalence under pipeline and latency shifts, post-synthesis RTL-to-gate closure, and robust debug strategy for ECO, retiming, and clock-gating transformations.

How to study this section

  1. Start with each topic hub and restate the requirement intent in your own words.

  2. Use reports and debug pages to classify first divergence accurately.

  3. Practice worked examples and interview drills with fixed run metadata.

  4. Close with checklist and residual-risk framing before signoff claims.

Topics

  1. combinational-lec/ - Combinational LEC: Key-Point Matching and Structural Normalization

  2. sequential-equivalence/ - Sequential Equivalence: Latency-Aware Proofs Across Micro-Architectural Changes

  3. rtl-to-gate-lec/ - RTL-to-Gate LEC: Post-Synthesis Signoff and Constraint Hygiene

  4. eco-and-retiming-checks/ - ECO, Retiming, and Clock-Gating Checks: Non-Equivalence Debug to Root Cause

Related topics

Formal deep dive

Equivalence confidence comes from transformation-aware setup and rapid first-divergence diagnosis.

Concept diagram

diagram
EQUIVALENCE WORKFLOW

golden and revised design -> mapping and alignment -> mismatch triage -> closure evidence

Metric graph

diagram
LEC/SEC DEBUG SIGNALS

setup mismatches        █████
real behavioral deltas  ███
resolved divergences    ███████

Metrics and artifacts to collect

  • compare-point match quality

  • SEC latency-alignment success

  • RTL-to-gate variant coverage

  • ECO mismatch root-cause aging

Mini case study

A late ECO mismatch was traced to clock-gating setup, then closed with repeatable SEC alignment rules.

Debug branches

  • Classify mismatch source before editing waiver sets.

  • Use SEC when latency movement is intentional.

  • Replay first divergence in simulation for cross-validation.

Senior review question

Ask: which requirement intent is proven, under which assumptions, and what residual risk remains?

Practice this lesson