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Course contents

  • How to Use This Course
  • Reading Paths
  • Glossary
  • Metrics Reference
  • Formal Cheat Sheet
  • Formal Foundations19
  • Properties and SVA16
  • Property Development and Constraints19
  • Proof Engines and Convergence23
  • Formal Applications20
  • Equivalence Checking14
    • Combinational Equivalence and the Miter
      • Miter Construction
      • SAT Sweeping and Structural Hashing
      • Constants, Don't-Cares and Constrained Equivalence
      • Reading a Failing Miter
    • Sequential Equivalence
    • RTL to Gate: What LEC Assumes
    • ECO and Alternative-Implementation Checks
  • Formal Coverage and Signoff15
  • Methodology and Debug13
  • Interview Prep15
  • Capstone: A Chip-Block Verification Lab24
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←Equivalence Checking
  1. Topics
  2. Formal Verification
  3. Equivalence Checking
  4. Combinational Equivalence and the Miter

Part 6 of 10Part 6 of 10/Equivalence CheckingAll levels

Combinational Equivalence and the Miter

Two combinational blocks, one shared input vector, one comparator: the miter and what its verdict means.

  • 4topics
  • 4lessons

Two adders leave two different tools and land in the same netlist. The synthesis report says they match, but the report is a claim, not a proof. This topic builds the proof: the miter that turns equivalence into one safety property, the solver technique that scales it, the constrained form that weakens it honestly, and the reading discipline for the day the comparator fires.

Lesson

After it you can...

Miter Construction

Build a miter from two blocks, prove it, and read the mismatch trace.

SAT Sweeping and Structural Hashing

Explain how shared structure and candidate signatures make a big miter solvable.

Constants, Don't-Cares and Constrained Equivalence

State a constrained result exactly and prove every mode.

Reading a Failing Miter

Tell a real mismatch from a setup difference and minimise the trace.

Suggested order: top to bottom. Build the miter, learn why it scales, learn the weaker constrained form, then practise reading failures. The synthesis-side flow this complements lives at Combinational Equivalence.

Shared inputs drive two cones whose outputs are compared bit by bit with XOR gates; the XOR results are ORed together and the single property asserts that output is never 1.
A miter: shared inputs feed both cones, per-bit XOR feeds one OR, and the property asserts the output never goes high.
Check yourself Why must the two cones share exactly the same input wires rather than two copies driven alike?

Two copies are two independent choices to the solver: it could drive them differently and report a mismatch no real stimulus can produce. Shared wires force one stimulus into both cones, so every counterexample is replayable.

Draw this diagram from memory before the interview: shared inputs, two cones, XOR, OR, one assertion. Most equivalence questions can be answered by pointing at one of its five parts.

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See also

  • Sequential Equivalence
  • RTL to Gate: What LEC Assumes
  • ECO and Alternative-Implementation Checks