The synthesis flow hands over a netlist and a passing comparison, and the signoff treats the RTL proof as proven for silicon. That transfer is sound only under assumptions nobody simulated: every flop matched one-to-one, scan and test disabled, constants identical, reset the same. This topic lists those assumptions, shows the false pass or false fail each one produces, and draws the line where one-to-one comparison stops working.

Suggested order: top to bottom. Assumptions first, because everything else is a footnote to them; key points next, because unmapped state is the most common finding; limits last, because it tells you when to stop using the method. The flow view this complements lives at Equivalence Checking.