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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
    • Testbench Debug Puzzles: Why Did the Test Hang?
    • Deadlock Scenario Puzzles: Objection and Phase Stalls
    • Scoreboard Puzzles: Mismatch or Ordering Bug?
      • Out-of-Order Responses Miscompared as Corruption
      • Missing First Transaction After Reset
      • Duplicate Transactions from Handle Reuse
      • Mismatch Cascade After One Lost Item
      • End-of-Test Draining Missing
      • Duplicate Expected Entries from Predictor Retry Path
    • Real Interview Rounds: End-to-End Debug Walkthrough
    • Scenario & Debug Puzzles: Tricky Q&A
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Scoreboard Puzzles: Mismatch or Ordering Bug?
  1. Topics
  2. DV Interview Puzzles
  3. Scenario & Debug Puzzles
  4. Scoreboard Puzzles: Mismatch or Ordering Bug?
  5. End-of-Test Draining Missing
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    VLSI DV Interview PuzzlesAll levels

    End-of-Test Draining Missing

    Random tests fail with 'expected queue not empty' in about 2% seeds. DUT has variable response latency and can legally return after stimulus stops.

    Puzzle

    Difficulty: Medium · Puzzle 5 of 6 · Topic: Scoreboard Puzzles: Mismatch or Ordering Bug?

    Random tests fail with 'expected queue not empty' in about 2% seeds. DUT has variable response latency and can legally return after stimulus stops.

    Code

    design.sv
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    task run_phase(uvm_phase phase);
      forever begin
        compare_once();
      end
    endtask
    
    function void check_phase(uvm_phase phase);
      if (exp_q.size() != 0 || got_q.size() != 0)
        \`uvm_error("SB", "leftover transactions");
    endfunction

    Hint

    A scoreboard needs explicit drain policy when response latency is elastic.

    Step-by-step solution

    Diagram
    1) Log queue sizes near end-of-test and observe they are shrinking but not yet zero.
    2) Confirm no drain window exists between stimulus completion and final check.
    3) Implement phase_ready_to_end wait/drain with bounded timeout and progress checks.
    4) Keep objection until queues settle or timeout indicates real hang.
    5) Track residual ids in timeout message for actionable debug.

    Answer

    Answer: Bug: scoreboard checks leftovers immediately without allowing legal late responses to drain. Fix: add bounded end-of-test draining before final emptiness assertion.

    How this was checked

    Checked by running the code in Verilator 5; the printed output supports the answer above. Plain-SV model of elastic latency: an immediate check sees 3 leftovers, a progress-based drain sees none, and a truly lost response still times out.

    Why candidates get it wrong

    Removing the check hides escapes; the right fix is controlled drain, not silence.

    Interviewer follow-up

    What timeout heuristic would you use so drain does not mask real deadlocks? Model answer: Bound it by the spec's maximum response latency times a margin, measured from the last progress event: restart the timer whenever the queue size changes, so a slow-but-moving drain continues while a stuck one fails after one latency window with the residual ids in the message.

    Say it out loud

    First I check whether the leftover entries are late legal responses or truly lost ones, by looking at when the check runs relative to the last traffic. The root cause is that the scoreboard checks for leftovers immediately, without letting legal late responses drain. I confirm it by delaying the check and seeing the leftovers disappear. The fix is a bounded end-of-test drain before the final emptiness check, not removing the check.

    Related topics

    • End-of-Test Checks: What Must Be Empty Before a Test Passes

    • End-of-Test Chain: Extract, Check, Report and Final

    • Back to Scoreboard Puzzles: Mismatch or Ordering Bug?

    • Scenario & Debug Puzzles section

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    See also

    • Out-of-Order Responses Miscompared as Corruption
    • Missing First Transaction After Reset
    • Duplicate Transactions from Handle Reuse