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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
    • Event Scheduling Puzzles
    • Race Condition Puzzles
      • Competing Active Writers on x
      • Blocking Writer vs NBA Writer Same Signal
      • Reading q Before the NBA (Not a Race)
      • Fork join_none Loop Variable Capture and kill()
      • Lost Update in Forked Counter
      • Two always_ff Writers, One Register
    • Clocking Block Puzzles
    • Semaphore & Mailbox Puzzles
    • Concurrency & Timing Puzzles: Tricky Q&A
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Race Condition Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Concurrency & Timing Puzzles
  4. Race Condition Puzzles
  5. Competing Active Writers on x
On this page

    VLSI DV Interview PuzzlesAll levels

    Competing Active Writers on x

    Predict post-NBA values of x and y on each edge. Is behavior deterministic across simulators?

    Puzzle

    Difficulty: Medium · Puzzle 1 of 6 · Topic: Race Condition Puzzles

    Predict post-NBA values of x and y on each edge. Is behavior deterministic across simulators?

    Code

    tb.sv
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    module tb;
      bit clk = 0;
      int x = 0;
      int y = 0;
    
      always #5 clk = ~clk;
    
      always @(posedge clk) begin
        x = x + 1;
        y <= x;
      end
    
      always @(posedge clk) begin
        x = x + 10;
      end
    
      initial begin
        repeat (2) begin
          @(posedge clk);
          $strobe("[%0t] x=%0d y=%0d", $time, x, y);
        end
        #1 $finish;
      end
    endmodule

    Hint

    Both blocks write x in active with no ordering guarantee.

    Step-by-step solution

    Diagram
    1) x ends each edge as old_x + 11 regardless of order.
    2) y<=x samples x in whichever intermediate active state Process A sees.
    3) If A runs first on first edge, y becomes 1; if B runs first, y becomes 11.
    4) Same ambiguity repeats each edge, so y is race-dependent.

    Answer

    Answer: x is deterministic per edge (+11), but y is nondeterministic because it samples race-dependent active-state x before NBA update.

    How this was checked

    Checked by running the code in Verilator 5 and Icarus Verilog 13; the printed output supports the answer above. x is +11 per edge in any order; y here comes from one legal process order (the other order gives y=12 at t=15). Icarus runs the two writers in the other order, so x is identical but y differs at t=15: the LRM leaves the order undefined.

    Why candidates get it wrong

    Using NBA on y does not sanitize the active-region race on x.

    Interviewer follow-up

    How would you refactor to a single writer while preserving intended math?

    Say it out loud

    The x result is deterministic, plus eleven per edge, but y is not. Both blocking writers run in Active in an order the LRM does not define, and y takes x from whatever intermediate state its process sees, so y can be 1 or 11 on the first edge. The trap is thinking the NBA on y cleans it up, when the race is on x before the NBA. I would remove the second writer or fix the ordering, and check with a different tool or a source reorder.

    Related topics

    • Anatomy of a TB/RTL Race

    • Blocking vs Nonblocking Assignments

    • Hunting X's and Races

    • Back to Race Condition Puzzles

    • Concurrency & Timing Puzzles section

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    See also

    • Reading q Before the NBA (Not a Race)
    • Fork join_none Loop Variable Capture and kill()
    • Lost Update in Forked Counter