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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
    • Event Scheduling Puzzles
      • Assertion Samples Preponed Values
      • Does #0 Beat NBA?
      • Trigger Then Wait: The Missed Event
      • Program Drive Is Seen One Edge Later
      • Last NBA in a Process Wins
      • Assertion Action Block Cannot Rewind Edge
    • Race Condition Puzzles
    • Clocking Block Puzzles
    • Semaphore & Mailbox Puzzles
    • Concurrency & Timing Puzzles: Tricky Q&A
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Event Scheduling Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Concurrency & Timing Puzzles
  4. Event Scheduling Puzzles
  5. Last NBA in a Process Wins
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    VLSI DV Interview PuzzlesAll levels

    Last NBA in a Process Wins

    Predict active print and end-of-slot value of q on the first edge. Explain why only one NBA survives.

    Puzzle

    Difficulty: Easy · Puzzle 5 of 6 · Topic: Event Scheduling Puzzles

    Predict active print and end-of-slot value of q on the first edge. Explain why only one NBA survives.

    Code

    tb.sv
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    module tb;
      bit clk = 0;
      int q = 0;
      always #5 clk = ~clk;
    
      always @(posedge clk) begin
        q <= 1;
        q <= 2;
        q <= 3;
        $display("[%0t ACTIVE] q=%0d", $time, q);
      end
    
      initial begin
        @(posedge clk);
        $strobe("[%0t POSTPONED] q=%0d", $time, q);
        #1 $finish;
      end
    endmodule

    Hint

    Within one process and one time slot, later NBA to same variable overrides earlier NBA updates.

    Step-by-step solution

    Diagram
    1) Active print sees old q=0 at t=5.
    2) Three NBAs are queued for q in same process.
    3) Last assignment q<=3 overrides earlier q<=1 and q<=2 for that slot.
    4) Postponed print shows q=3 at t=5.
    5) The #1 before $finish keeps the strobe (Postponed region) out of the time slot where $finish runs, so every tool prints it.

    Answer

    Answer: Active shows q=0 at t=5; final value is q=3 at t=5. Last NBA to same variable in the process wins.

    How this was checked

    Checked by running the code in Verilator 5 and Icarus Verilog 13; the printed output supports the answer above. Only the last NBA to q in the process survives: the final value is 3. Icarus agrees: the active print is the old q=0 and the end-of-slot value is 3.

    Why candidates get it wrong

    People mix this with cross-process NBA ordering, which is not guaranteed.

    Interviewer follow-up

    What if each q<= assignment were in separate always blocks on the same edge?

    Say it out loud

    The first print in Active shows the old q, which is 0, because NBAs have not been applied yet. Three NBAs to q from the same process are queued in order and the last one wins, so q ends at 3. The trap is mixing this with NBAs from different processes, where the order is not defined. I would check the strobe is not in the same slot as the finish, so every tool prints it.

    Related topics

    • Blocking vs Nonblocking Assignments

    • The Event Scheduler & Stratified Regions

    • Back to Event Scheduling Puzzles

    • Concurrency & Timing Puzzles section

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    See also

    • Assertion Samples Preponed Values
    • Does #0 Beat NBA?
    • Trigger Then Wait: The Missed Event