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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
    • Event Scheduling Puzzles
    • Race Condition Puzzles
    • Clocking Block Puzzles
      • Why Every Sample Is One Cycle Old
      • Interpreting |=> ##1 in Clocking Domain
      • disable fork Kills Unrelated Background Threads
      • input #0 vs input #1step Snapshot
      • Nonzero Input Skew Looks Back in Time
      • Mixing Direct Drive and cb Drive
    • Semaphore & Mailbox Puzzles
    • Concurrency & Timing Puzzles: Tricky Q&A
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Clocking Block Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Concurrency & Timing Puzzles
  4. Clocking Block Puzzles
  5. input #0 vs input #1step Snapshot
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    VLSI DV Interview PuzzlesAll levels

    input #0 vs input #1step Snapshot

    Two monitors sample the same grant with different input skews. Which one sees the same-edge NBA-updated grant? All signals are initialised so the answer does not depend on 2-state or 4-state.

    Puzzle

    Difficulty: Medium · Puzzle 4 of 6 · Topic: Clocking Block Puzzles

    Two monitors sample the same grant with different input skews. Which one sees the same-edge NBA-updated grant? All signals are initialised so the answer does not depend on 2-state or 4-state.

    Code

    ifc.sv
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    `timescale 1ns/1ns
    interface ifc(input bit clk);
      logic req = 1;
      logic grant = 0;
      clocking mon0 @(posedge clk);
        default input #0;
        input grant;
      endclocking
      clocking mon1 @(posedge clk);
        default input #1step;
        input grant;
      endclocking
      always @(posedge clk) grant <= req;
    endinterface
    
    program automatic check(ifc vif);
      initial begin
        @(vif.mon0);
        $display("[%0t] mon0.grant=%0b mon1.grant=%0b", $time, vif.mon0.grant, vif.mon1.grant);
        $finish;
      end
    endprogram
    
    module tb;
      bit clk = 0;
      always #5 clk = ~clk;
      ifc vif(clk);
      check c(vif);
    endmodule

    Hint

    input #0 samples after the NBAs (Observed region); input #1step samples before the edge (Preponed).

    Step-by-step solution

    Diagram
    1) At t=5 the interface's always block reads req=1 and queues grant<=1.
    2) mon1 (#1step) holds the Preponed value of grant: 0.
    3) mon0 (#0) is sampled in the Observed region, after the NBA committed: 1.
    4) The reader is a program (Reactive region), so it runs after both samples exist and the result is the same in every tool. Verilator prints mon0.grant=1 mon1.grant=0.

    Answer

    Answer: mon0.grant=1 and mon1.grant=0 at t=5. Skew choice changes which side of the NBA you sample.

    How this was checked

    Checked by running the code in Verilator 5; the printed output supports the answer above. input #0 sees the post-NBA grant (1), input #1step sees the pre-edge value (0).

    Why candidates get it wrong

    Using #1step 'for safety' gives the pre-edge value, i.e. one cycle stale for flopped DUT outputs. And do not read these from a module initial and call the result portable: the wake-up region of @(clocking event) is only guaranteed late enough in a program.

    Interviewer follow-up

    Which skew is better for scoreboard checks against flopped DUT outputs and why? Model answer: #1step (Preponed) is the usual default because it is race-free and matches what a synchronous DUT register would have captured at that edge; #0 also reflects NBA results but depends on reading after Observed and is fragile across mixed module/program code.

    Say it out loud

    Mon0 sees the new grant, 1, and mon1 sees the old one, 0. The input skew of #1step takes the Preponed value from before the NBA, while #0 samples in Observed, after the NBA has committed. So the skew choice decides which side of the NBA you sample. The trap is using #1step for safety, which gives a one-cycle-old value for flopped DUT outputs. I would also read it from a program, because a module initial does not guarantee a late enough wake-up.

    Related topics

    • Clocking Blocks

    • Clocking Blocks as the Cure

    • Driving & Sampling via Clocking Blocks

    • Back to Clocking Block Puzzles

    • Concurrency & Timing Puzzles section

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    See also

    • Why Every Sample Is One Cycle Old
    • Interpreting |=> ##1 in Clocking Domain
    • Mixing Direct Drive and cb Drive