Memory Model to Protocol Mapping: Review Checklist

Review checklist

Review Checklist for Memory Model to Protocol Mapping explains how to reason from coherency invariant to measurable engineering decision.

• Invariant and ordering assumptions are written explicitly.

• Primary metric tracked: ordering litmus pass rate across mode matrix.

• Primary artifact linked: litmus dashboard + fence-propagation trace.

• Owners confirmed: architecture, firmware, verification.

• Regression matrix includes stress and mixed-workload runs.

Cache coherency deep dive

Cache coherence is a correctness contract across caches, interconnect, and software ordering.

Concept diagram

requester -> coherence fabric -> owner or memory -> state update

Metric graph

traffic mix across request, snoop, response, data

Metrics and artifacts to collect

• coherence latency

• invalidation rate

• retry rate

• stale-read incidents

Mini case study

Anchor debug to first stale read and the exact line state transition.

Debug branches

• Track ownership

• Track ordering

• Track evidence

Senior review question

Ask: what is the first line state transition that deviates, and which ordering rule does it break?

Key takeaways

• Tie every coherency claim to one cache line, one transaction identity, and one measurable counter.

• Keep proof artifacts from simulation and silicon replay aligned by address, state, and ordering event.

Common pitfalls

• Chasing bandwidth regressions without checking false sharing and line bouncing first.

• Assuming coherence correctness implies memory consistency correctness.

• Declaring closure without litmus, stress, and post-silicon replay evidence.