Memory Subsystem Integration

Module objective

Coherency interactions with LLC, DRAM controller policy, and IO pathways.

• Focus on mechanism-level reasoning over memorized templates.

• Map every claim to a measurable metric and artifact.

• Practice staff-grade communication through structured review language.

Topics

1. llc-inclusivity-exclusivity-policies/ — LLC Inclusivity and Exclusivity Policies

2. dram-scheduling-effects-on-coherency/ — DRAM Scheduling Effects on Coherency

3. io-coherency-and-device-agents/ — IO Coherency and Device Agents

Related topics

• Cache Coherency course hub

Cache coherency deep dive

Cache coherence is a correctness contract across caches, interconnect, and software ordering.

Concept diagram

requester -> coherence fabric -> owner or memory -> state update

Metric graph

traffic mix across request, snoop, response, data

Metrics and artifacts to collect

• coherence latency

• invalidation rate

• retry rate

• stale-read incidents

Mini case study

Anchor debug to first stale read and the exact line state transition.

Debug branches

• Track ownership

• Track ordering

• Track evidence

Senior review question

Ask: what is the first line state transition that deviates, and which ordering rule does it break?