Cache Coherency · All levels
LLC Inclusivity and Exclusivity Policies: Comparison Matrix
Comparison Matrix for LLC Inclusivity and Exclusivity Policies.
Comparison matrix
Comparison Matrix for LLC Inclusivity and Exclusivity Policies explains how to reason from coherency invariant to measurable engineering decision.
OWNERSHIP MATRIX — LLC Inclusivity and Exclusivity Policies
+---------------------+-----------------------------+------------------------------+
| Team | Primary accountability | Typical evidence |
+---------------------+-----------------------------+------------------------------+
| architecture | protocol semantics | architecture spec + rationale|
| performance | implementation correctness | waveform + state trace |
| rtl | closure and reproducibility | checker/coverage + dashboards|
+---------------------+-----------------------------+------------------------------+Choose options by failure-mode containment and operational debuggability, not by one benchmark number.
Cache coherency deep dive
Cache coherence is a correctness contract across caches, interconnect, and software ordering.
Concept diagram
requester -> coherence fabric -> owner or memory -> state updateMetric graph
traffic mix across request, snoop, response, dataMetrics and artifacts to collect
coherence latency
invalidation rate
retry rate
stale-read incidents
Mini case study
Anchor debug to first stale read and the exact line state transition.
Debug branches
Track ownership
Track ordering
Track evidence
Senior review question
Ask: what is the first line state transition that deviates, and which ordering rule does it break?
Key takeaways
Tie every coherency claim to one cache line, one transaction identity, and one measurable counter.
Keep proof artifacts from simulation and silicon replay aligned by address, state, and ordering event.
Common pitfalls
Chasing bandwidth regressions without checking false sharing and line bouncing first.
Assuming coherence correctness implies memory consistency correctness.
Declaring closure without litmus, stress, and post-silicon replay evidence.