UVM Coding Practice · Senior

Sequence Library Arbitration

Weighted random sequence pick from library.

Interview prompt

Configure uvm_sequence_library with three stress sequences and weights.

diagram
WHITEBOARD CHAIN

1. DECLARE    interfaces / types / ports you need
2. SKELETON   class extends + utils macro + key methods
3. MECHANISM  fill one critical method while narrating
4. PITFALL    name one bug juniors make on this pattern
5. TEST       how you would smoke-test the component

Reference sketch (≤40 lines)

systemverilog
class my_seq_lib extends uvm_sequence_library #(pkt);
  `uvm_object_utils(my_seq_lib)
  `uvm_sequence_library_utils(my_seq_lib)
  function void new(string name="lib");
    super.new(name);
    init_sequence_library();
    add_sequence(pkt_stress_seq::get_type(), 3);
    add_sequence(pkt_idle_seq::get_type(), 1);
    add_sequence(pkt_err_seq::get_type(), 2);
  endfunction
endclass

add_sequence with weight, init_sequence_library, execute on sequencer in test main_phase or via default_sequence config.

Mechanism to narrate

  • Library rand-picks child sequence type by weight

  • Use for stress mix without one giant random seq

  • Weights control error vs idle vs stress ratio

Smoke test (5 minutes)

  • Run 100 iterations — log distribution roughly matches weights.

  • Zero weight seq never selected.

Common pitfalls

  • Forget init_sequence_library.

  • No weights — uniform unwanted mix.

  • Library on wrong sequencer.