UVM Coding Practice · Senior

Layered Virtual Sequence

Virtual sequence starting child sequences on sub-sequencers.

Interview prompt

Virtual seq runs cfg seq on reg sequencer and traffic seq on bus sequencer.

diagram

WHITEBOARD CHAIN

1. DECLARE    interfaces / types / ports you need
2. SKELETON   class extends + utils macro + key methods
3. MECHANISM  fill one critical method while narrating
4. PITFALL    name one bug juniors make on this pattern
5. TEST       how you would smoke-test the component

Reference sketch (≤40 lines)

systemverilog

class vseq extends uvm_sequence;
  virtual task body();
    cfg_seq c = cfg_seq::type_id::create("c");
    pkt_seq p = pkt_seq::type_id::create("p");
    c.start(p_sequencer.cfg_sqr);
    p.start(p_sequencer.bus_sqr);
  endtask
endclass

Key takeaways

Name which sequencer each child starts on.

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