UVM Coding Practice · Senior

Senior UVM Coding Cheat Sheet

One-page patterns: macros, phases, config_db, TLM, sequences, scoreboard, RAL, factory, pitfalls.

Class macros

systemverilog

`uvm_component_utils(my_comp)
`uvm_object_utils(my_item)
`uvm_declare_p_sequencer(my_sqr)
`uvm_field_int(addr, UVM_ALL_ON)

Phases + objections

diagram

build → connect → end_of_elaboration → start_of_simulation
→ run (reset/configure/main/shutdown) → extract → check → report

task run_phase(uvm_phase phase);
  phase.raise_objection(this);
  // stimulus
  phase.phase_done.set_drain_time(this, 100);
  phase.drop_objection(this);
endtask

config_db

systemverilog

uvm_config_db#(apb_vif)::set(this, "env.agent*", "vif", vif);
uvm_config_db#(apb_vif)::get(this, "", "vif", vif);
uvm_config_db#()::dump();

TLM

systemverilog

uvm_analysis_port #(txn) ap;
uvm_analysis_imp_act #(txn, sb) act_imp;
mon.ap.connect(sb.act_imp);

Sequence body

systemverilog

virtual task body();
  repeat (N) begin
    pkt req = pkt::type_id::create("req");
    start_item(req);
    assert(req.randomize());
    finish_item(req);
  end
endtask

Scoreboard analysis imp

systemverilog

function void write_act(txn t);
  act_q.push_back(t);
  if (exp_q.size()) compare(exp_q[0], act_q[0]);
endfunction

Reg adapter skeleton

systemverilog

virtual function void reg2bus(uvm_reg_item rw, ref bus_txn bus);
  bus.addr = rw.addr;
  bus.data = rw.data[0];
  bus.write = (rw.kind != UVM_READ);
endfunction

Factory override

systemverilog

pkt::type_id::set_type_override(derived_pkt::get_type());
// BEFORE create of pkt

Top 10 interview pitfalls

config_db path typo → null vif
Missing item_done → seq hang
Objection leak → sim never ends
Factory override after create
Head-only scoreboard on OOO bus
reg2bus vs bus2reg reversed
Compare before reset flush
analysis port not connected
Silent whiteboard — no narration
No smoke test after sketch

Key takeaways

Print or copy this page before mock interviews.
Pair with Code lab level 8–10 drills.

Practice this lesson