UVM Coding Practice · Senior

Monitor Reconstruct Beat

Byte lanes, valid/ready, packing one protocol beat into a txn.

Interview prompt

Reconstruct one APB read beat from PSEL/PENABLE/PREADY signals into an apb_txn.

diagram
WHITEBOARD CHAIN

1. DECLARE    interfaces / types / ports you need
2. SKELETON   class extends + utils macro + key methods
3. MECHANISM  fill one critical method while narrating
4. PITFALL    name one bug juniors make on this pattern
5. TEST       how you would smoke-test the component

Reference sketch (≤40 lines)

systemverilog
task run_phase(uvm_phase phase);
  forever begin
    @(posedge vif.clk);
    if (vif.psel && !vif.penable) state = SETUP;
    if (state == SETUP && vif.penable && vif.pready) begin
      txn t = apb_txn::type_id::create("t");
      t.addr = vif.paddr; t.data = vif.prdata; t.write = 0;
      ap.write(t);
      state = IDLE;
    end
  end
endtask

Smoke test (5 minutes)

  • One read on bus — one analysis txn.

  • Wave matches txn fields.

Code lab drill

After reading, try Code lab exercise uvm-l8-int-monitor-beat — topic reference: /topics/uvm/coding-practice/monitor-driver/monitor-reconstruct-beat

Common pitfalls

  • Missing PREADY wait.

  • Sampling wrong clock edge.

  • No write bit on txn.