UVM Coding Practice · Senior

Monitor Protocol FSM

FSM states for monitor reconstruction.

Interview prompt

Draw monitor FSM for valid/ready handshake and where you emit txn.

diagram
WHITEBOARD CHAIN

1. DECLARE    interfaces / types / ports you need
2. SKELETON   class extends + utils macro + key methods
3. MECHANISM  fill one critical method while narrating
4. PITFALL    name one bug juniors make on this pattern
5. TEST       how you would smoke-test the component

Reference sketch (≤40 lines)

systemverilog
typedef enum { IDLE, WAIT_V, EMIT } mon_state_e;
mon_state_e state = IDLE;
// IDLE: wait valid
// WAIT_V: valid high, wait ready
// EMIT: valid && ready -> ap.write(txn); -> IDLE
  • IDLE → valid → WAIT_V → ready → EMIT txn

  • Reset forces IDLE; flush partial txn

  • Illegal combo → UVM_WARNING not silent drop

Mechanism to narrate

  • FSM on paper before run_phase code

  • Emit exactly one txn per completed handshake

  • Reset must clear state and optional partial txn buffer

Smoke test (5 minutes)

  • Draw FSM in 3 minutes without code.

  • Narrate where ap.write() is called.

Key takeaways

  • FSM on paper first — code second.