Two ways to hold a value

Both styles hold the register when idle. A clock enable reloads Q on every edge, so the clock tree keeps toggling, while a gated clock stops the edges.

The gated version below uses a plain latch plus AND for illustration. A production design uses the library's integrated clock-gating (ICG) cell, which is timed and tested as part of the clock tree. See the intentional latches lesson.

The picture has four slots per clock period: two while clk is high and two while it is low. A pulse cut short shows up as one high slot instead of two. The same en drives both gates, and it changes twice while clk is high.

• Bare AND gate: in g_naive, en falls one slot into the first high phase, so the gated clock is a runt pulse. Later en rises one slot into the second high phase, so a late short pulse appears. A flop clocked by either pulse can capture at the wrong moment.

• Latch-based gate: in g_icg, the latch holds en_lat steady while clk is high. The first pulse stays full width, the late enable does nothing, and en only takes effect after clk falls.

The ICG cell lesson runs the same two gates over six clock pulses and walks through each one.

When gating is worth it

Follow the questions from the top; every path starts from the same RTL, a register written with if (en).

• Default: the two cheap answers, a clock enable or tool-inserted ICG cells, need no change to the RTL style.

• Hand gating: only the bottom-right box adds clock-tree work, and it needs a measured power reason to get there.

• Fine grain, by the tool: in ASIC flows with clock gating turned on, synthesis turns if (en) register banks into ICG cells, down to banks of a few bits. The RTL stays a plain enable, and the tool makes the enable-or-gate choice per bank.

• Coarse grain, by hand: gating the clock of a whole idle block (for example 500 flops) also stops the clock-tree buffers feeding it. It is a candidate for a measured power comparison; confirm with power analysis.

• Power-sensitive designs where dynamic power in the clock tree is significant.

• FPGAs: use clock enables. The fabric has enable pins on its flops, and gating clocks in the fabric is avoided.

Common mistakes

• Glitches: if the enable can change while the clock is high, the gated clock can glitch. A latch (or ICG) prevents this.

• Skew: the gating cell sits on the clock path, so the clock tree must balance gated and ungated branches.

• Test: scan chains need the gate forced open in test mode.

• Verification: the enable timing relative to the clock is a real design constraint, not just logic.

Testbench

Both registers are checked against an independent expected-Q model, with directed load, hold and asynchronous reset cases followed by 40 random operations. Enable and data are driven 1 ns into the low phase and held through the next rising edge; reset is also asserted while the gate is closed.

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// 1) Clock enable: the usual, safe style
module reg_enable (input logic clk, rst_n, en, input logic [7:0] d, output logic [7:0] q);
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n)  q <= '0;
    else if (en) q <= d;
endmodule

// 2) Gated clock: a latch-based gate stops the clock edges
module reg_gated (input logic clk, rst_n, en, input logic [7:0] d, output logic [7:0] q);
  logic en_l, gclk;
  always_latch if (!clk) en_l = en;            // enable captured while the clock is low
  assign gclk = clk & en_l;                    // no edge reaches the flops when disabled
  always_ff @(posedge gclk or negedge rst_n)
    if (!rst_n) q <= '0;
    else        q <= d;
endmodule

Related topics

• Clock gating in the timing section