A long chain of logic limits the clock rate. Pipelining cuts it with registers, so each stage does part of the work while several items are in flight.
5 lessons, about 19 min
Throughput: 1 result per ns (10⁹ results/s). Latency: 4 cycles = 4 ns from input to the corresponding output.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Throughput and Latency
With S balanced stages the period falls toward D/S plus register overhead.
Latency in time barely changes and can grow; the gain is throughput over a stream.
The slowest stage sets the clock, and a loop such as acc <= acc + x cannot simply gain stages.
A Three-Stage Arithmetic Pipeline
Give the slow multiply its own stage; the add then has slack.
Delay each late operand by the same number of stages as the data it belongs with.
Reset only the valid bits; consumers ignore y while out_v is low.
Valid/Ready Flow Control
A transfer happens on an edge where both valid and ready are high.
Once valid is asserted it stays asserted, with data stable, until the transfer.
in_ready = !out_valid || out_ready keeps one item per cycle, but a stall ripples back combinationally through a chain.
Rule of thumb: never drop an item because ready was low, and never copy it because the consumer stalled.
Pipelined MAC
Delay valid and frame markers by the same number of stages as the data.
Count accepted products, not clock cycles. Reset validity and frame state, not every wide data register.
The accumulator is a loop-carried add, so its adder path sets the clock; partial sums or interleaving break it.
Precision Verification
Test one LSB below, at and above every rounding and saturation boundary, with ties of both signs.
The bit-exact model proves conformance; the high-precision model measures accuracy against the budget.
At a tie both neighbours are half an LSB away, so only the bit-exact compare catches a wrong tie rule.
Rule of thumb: mutate the rounding, a shift and a valid delay, and confirm the testbench fails.
Mini project: a programmable timer with prescaler, compare and interrupt
Code lab: Pipeline register stage
Practice question: Design a 3-stage pipelined ALU with stall support
Code lab: Pipelined multiplier stage
Practice question: Two-stage valid/ready pipeline: throughput, latency and backpressure
Interview: run a mock interview on this topic