Place and route can buffer, size and move cells. It cannot shorten a route the architecture made long, split a net the RTL made global, or spread a cone the RTL wrote as one lump. Wide buses, chip-wide fanout and late muxing are RTL decisions, and they show up as wire length and congestion.
Structure | Physical cost | RTL response |
|---|---|---|
Long routes across the chip | Route delay lands on the timing path | Pipeline the route with a register slice |
One net fanning out chip-wide | A deep buffer tree with skew to close | Replicate the register near each cluster |
A flat giant logic cone | Potential logic/routing concentration | Evaluate hierarchy, preservation and placement controls against reports |
This is a concept sketch, not an implementation result. Read the two panels as the same function with a different net structure.
Before: one net reaches every corner. The tool must build one buffer tree spanning the die and balance its skew.
After: each replica sits beside its cluster, so its tree stays local. The long leg to the right now drives two flops, not a tree, and a slice splits it in half.
Cost: the slice adds a cycle to the right-hand replicas, so the left ones need the same delay to stay aligned.
Suppose the enable feeds 4 clusters of 256 flops, 1024 loads in all, and, only for this arithmetic, that the tool keeps each buffer to a fanout of 8.
Structure | Loads per driver | Buffer levels | Wire span |
|---|---|---|---|
One en_q | 1024 | 4 (8^3 = 512 is too few, 8^4 = 4096 is enough) | The whole die |
A replica per cluster | 256 | 3 (8^2 = 64 is too few, 8^3 = 512 is enough) | One cluster |
Replication saves a level of buffering and, more importantly, keeps every tree inside one cluster. The four legs from en_q to the replicas still exist, but each drives one flop and can be registered. The testbench below models that registered version: two replicas, two stages, two cycles of latency.
No. Synthesis may merge identical registers, and RTL does not fix their placement. Review duplication/preservation settings, the mapped netlist, fanout, placement and timing reports.
It may create deep logic and centralized routing. Hierarchy suggests partition intent but does not constrain placement: synthesis may flatten it. Review supported hierarchy-preservation controls, placement regions and path reports before claiming better closure.
Locality is a hypothesis, not a consequence of RTL grouping. Coordinate hierarchy preservation and physical regions with synthesis/PnR owners, then compare mapped topology and routed QoR under the controlled comparison standard. Preserve only boundaries that help the measured design; constraints can also inhibit optimization.
A two-level functional fanout model with two register stages. This adds pipeline latency rather than demonstrating timing-neutral duplication; the interface must permit that delay. Production duplication needs flow-specific preservation/placement controls and before/after implementation reports.
`timescale 1ns/1ps
module fanout_tree (
input logic clk,
input logic rst_n,
input logic en_src,
output logic en_a0,
output logic en_a1,
output logic en_b0,
output logic en_b1
);
logic en_q0, en_q1;
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
en_q0 <= 1'b0;
en_q1 <= 1'b0;
en_a0 <= 1'b0;
en_a1 <= 1'b0;
en_b0 <= 1'b0;
en_b1 <= 1'b0;
end else begin
en_q0 <= en_src;
en_q1 <= en_src;
en_a0 <= en_q0;
en_a1 <= en_q0;
en_b0 <= en_q1;
en_b1 <= en_q1;
end
end
endmodule
The floorplan figure is a concept sketch and the buffer-level table is arithmetic under an assumed maximum fanout of 8; neither is an implementation result.
The testbench checks latency and replica alignment only. The model adds pipeline latency; it does not demonstrate timing-neutral duplication. Production duplication needs flow-specific preservation and placement controls, and before and after implementation reports.