Senior RTL engineers expose clean partition boundaries aligned to floorplan blocks: explicit interfaces, documented clock/reset ownership, and optional register-slice insertion points. Physical partitions and reset domains need not coincide.
Hook | Rule |
|---|---|
Ingress and egress register stage | Every block boundary offers a flop the backend can use |
Valid and data cross together | The qualifier travels with the word, never beside it |
Reset ownership | Shared or independent according to architecture; release timing and recovery contracts are explicit |
Compile-time slice parameter | Ports stay the same; latency and reset behavior change and require consumer agreement |
The boundary below carries a valid bit with its word. USE_SLICE chooses a registered crossing or a combinational one, and the interface is identical either way.
Configuration | Timing contract | Reset contract |
|---|---|---|
USE_SLICE=0 | Combinational; E0 launch settles before E1 consumer edge | Bypass ignores reset; producer must suppress valid during reset |
USE_SLICE=1 | E0 launch captured at E1; output available after E1, consumed at E2 | Asynchronous clear cancels valid and clears data; release follows domain reset policy |
Each slot shows the values sampled at one rising edge, numbered from 0. out_data_s0 is the bypass (USE_SLICE = 0) and out_data_s1 the slice (USE_SLICE = 1); the valid outputs follow the same pattern.
Slot 1: reset is still asserted, yet the bypass already shows 1234. The slice is held at 0. This is the reset difference in the table.
Slot 2: reset releases and C000 is offered. The bypass shows it in the same slot; the slice captures it at this edge.
Slots 3 to 5: the slice shows C000, C001, C002, each one slot after the bypass: one cycle of latency.
Slot 6: both are 0 once nothing is offered and the last word has drained.
Both configurations assume an always-accepting sink in the same clock domain. This parameter is not behaviorally transparent, a CDC mechanism, or an elastic ready/valid slice. Carry latency in the integration contract; use storage and coordinated backpressure for stalled consumers.
Inside one block, where the route stays short. Across partitions the registered slice carries the crossing.
No. Shared reset can be intentional for interacting logic. Each clock domain still needs appropriate release synchronization and reset-tree timing. Independent reset is required only by the architecture; if introduced, define isolation, outstanding-transaction cancellation/recovery and readiness before traffic resumes.
A finite checker observes the bypass before capture, the sliced output after capture, and the reset difference. The two configurations are not equivalent: their latency and reset contracts differ.
`timescale 1ns/1ps
module block_boundary #(
parameter int DW = 32,
parameter int USE_SLICE = 1
) (
input logic clk,
input logic rst_n,
input logic valid_in,
input logic [DW-1:0] data_in,
output logic valid_out,
output logic [DW-1:0] data_out
);
generate
if (USE_SLICE) begin : g_slice
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
valid_out <= 1'b0;
data_out <= '0;
end else begin
valid_out <= valid_in;
data_out <= data_in;
end
end
end else begin : g_bypass
always_comb begin
valid_out = valid_in;
data_out = data_in;
end
end
endgenerate
endmodule
The checker observes the bypass before capture, the sliced output after capture, and the reset difference. It does not establish equivalence between the configurations, because their latency and reset contracts differ.