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Course contents

  • How to Use This Course
  • PD Flow Overview — RTL to GDSII
  • Data & Libraries — What PD Receives
  • Data and Libraries49
  • Floorplanning Expanded65
  • Power Planning57
  • Placement65
  • Clock Tree Synthesis57
  • Routing65
  • Timing Closure81
    • SDC for Implementation
    • Setup/Hold Closure Playbook
    • MCMM Signoff Strategy
    • ECO Timing Fixes
    • Path Group Prioritization
    • Generated Clocks and Clock Groups
      • Generated Clocks and Clock Groups — Mechanism
      • Generated Clocks and Clock Groups — Inputs & Outputs
      • Generated Clocks and Clock Groups — Reports & Metrics
      • Generated Clocks and Clock Groups — Debug Playbook
      • Generated Clocks and Clock Groups — Worked Example
      • Generated Clocks and Clock Groups — Pitfalls & Red Flags
      • Generated Clocks and Clock Groups — Interview Drills
      • Generated Clocks and Clock Groups — Review Checklist
    • IO Timing and Block Boundaries
    • Useful Skew in Timing Closure
    • Post-Route Extraction and SPEF
    • Timing Signoff Dashboard
    • Timing Closure Tricky Q&A
  • Signal Integrity and Variation41
  • Power Signoff57
  • Physical Verification65
  • Physical Design Integration49
  • Signoff and Tapeout49
  • PD Interview Prep5
  • PD Closure Cheat Sheet
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←Timing Closure
  1. Topics
  2. Physical Design
  3. Timing Closure
  4. Generated Clocks and Clock Groups
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    Physical DesignAll levels

    Generated Clocks and Clock Groups

    Generated Clocks and Clock Groups — physical design implementation and signoff.

    • 8topics
    • 8lessons

    Topics in this section

    1. 1Generated Clocks and Clock Groups — Mechanism1 lesson
    2. 2Generated Clocks and Clock Groups — Inputs & Outputs1 lesson
    3. 3Generated Clocks and Clock Groups — Reports & Metrics1 lesson
    4. 4Generated Clocks and Clock Groups — Debug Playbook1 lesson
    5. 5Generated Clocks and Clock Groups — Worked Example1 lesson
    6. 6Generated Clocks and Clock Groups — Pitfalls & Red Flags1 lesson
    7. 7Generated Clocks and Clock Groups — Interview Drills1 lesson
    8. 8Generated Clocks and Clock Groups — Review Checklist1 lesson

    On-call / interview prompt

    You own Generated Clocks and Clock Groups on a block nearing implementation freeze — what do you verify first?

    Diagram
    CLOSURE CHAIN
    
    1. METRIC     — name the failing report line (WNS, DRV, DRC count, IR %)
    2. HYPOTHESIS — 2–3 likely causes ordered by probability
    3. EXPERIMENT — one cheap check (corner, clock, report, map)
    4. FIX        — minimal physical or constraint change
    5. REGRESSION — what you re-run and what must not regress

    Topic overview

    Model derived clocks and asynchronous relationships correctly so timing math matches actual clocking architecture.

    Mechanism to narrate

    • Section: Timing Closure

    • Primary artifact: report_clock_timing + report_clock_groups consistency checks

    • Downstream dependency: next PD stage

    Staff/principal ownership model

    Own Generated Clocks and Clock Groups as a release decision, not a page of notes. A senior PD engineer names the metric, the physical mechanism, the cross-team dependency, and the smallest evidence-producing experiment.

    Diagram
    STAFF REVIEW MEMO — Timing Closure / Generated Clocks and Clock Groups
    
    1. Current state
       - Failing / watched metric: report_clock_timing + report_clock_groups consistency checks
       - Database tag, corner/mode, tool version: <fill before review>
       - Physical scope: block, hierarchy, macro region, clock domain, or net class
    
    2. Root-cause hypothesis
       - Most likely mechanism: <name physical or constraint mechanism>
       - Competing hypothesis: <name the second plausible cause>
       - Evidence still missing: <report/map/schematic/check>
    
    3. Proposed action
       - Minimal reversible fix: <physical, constraint, ECO, or methodology change>
       - Expected improvement: <metric delta>
       - Regression risk: late-stage schedule slip, silicon risk, or cross-stage regression
    
    4. Regression and signoff
       - Re-run: report_clock_timing + report_clock_groups consistency checks
       - Must not regress: timing, routing, power, PV, DFT, package, or tapeout signoff
       - Decision owner: PD owner

    Sub-lessons in this topic

    1. mechanism — Mechanism

    2. inputs-outputs — Inputs & Outputs

    3. reports — Reports & Metrics

    4. debug-playbook — Debug Playbook

    5. worked-example — Worked Example

    6. pitfalls — Pitfalls & Red Flags

    7. interview — Interview Drills

    8. checklist — Review Checklist

    Related topics

    • CDC intent and synchronizer assumptions

    • CTS clock topology alignment

    Key takeaways

    • Master Generated Clocks and Clock Groups through reports, not GUI habit.

    Deep dive: how this shows up in real closure

    Timing closure is a signoff matrix problem, not a single worst-path problem.

    Reports and artifacts to inspect

    • report_timing -max and -min with corner, mode, SI, and OCV enabled

    • path group WNS/TNS: which clock domain is actually blocking signoff

    • net delay percentage vs cell delay percentage

    • exception audit: false paths, multicycle paths, generated clocks

    Mini case study

    A -90 ps setup path has 75% net delay and crosses a macro channel. Sizing the launch flop is weak. The stronger response is to layer-promote or shorten the route, then re-run hold at the fast corner.

    Debug branches

    • If net delay dominates, look for physical fixes before cell sizing.

    • If cell delay dominates, consider VT swap, sizing, or RTL micro-architecture.

    • If only one mode fails, inspect mode-specific SDC overlays and case analysis.

    Senior review question

    Ask yourself: what single report line would prove this page's concept is either passing or failing?

    What changes at 10+ years

    • You are expected to predict what your fix can break before running it.

    • You should recognize when the issue is methodology, not one block's implementation.

    • You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

    Principal-level review bar

    Lesson pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

    What excellent looks like

    • Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

    • Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

    • Chooses experiments by information gain and reversibility, not by habit.

    • States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

    • Turns recurring failures into methodology guardrails, dashboards, or checklist items.

    Closure note template

    Diagram
    STAFF / PRINCIPAL CLOSURE NOTE
    
    Context:
      stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
      tag: <database / netlist / SDC / library stack>
      failing metric: <exact report line>
      affected scope: <block / hierarchy / path group / power domain / region>
    
    Hypotheses:
      H1: <most likely physical or constraint mechanism>
      H2: <competing explanation>
      H3: <methodology or input-data issue>
    
    Decision:
      next experiment: <cheap check that can falsify H1>
      fix candidate: <minimal reversible change>
      rollback trigger: <metric that says the fix is wrong>
      regression set: <timing / route / power / PV / DFT / package>
      escalation owner: <team or reviewer>

    Tradeoffs a senior engineer must discuss

    Technical tradeoff

    Timing closure is a signoff matrix problem, not a single worst-path problem. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

    Cross-team tradeoff

    • What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

    • Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

    • What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

    Leadership communication

    Diagram
    "The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

    Key takeaways

    • Always connect the concept back to a measurable signoff artifact.

    • A fix is not complete until you can name the regression checks.

    Common pitfalls

    • Optimizing by habit instead of reading the current report.

    • Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.

    PreviousNext: Leakage vs Dynamic Tradeoffs

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    Up nextLeakage vs Dynamic Tradeoffs

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    See also

    • SDC for Implementation
    • Setup/Hold Closure Playbook
    • MCMM Signoff Strategy