Physical Design — Implementation & Signoff

Who this is for

Target audience: physical design and implementation engineers (2–12+ YOE), RTL designers moving into PD, and interview candidates for timing closure / signoff roles. You need basic STA vocabulary — this course trains closure judgment : read reports, prioritize fixes, and defend tradeoffs through tapeout.

• Block owners closing place → route → signoff

• SoC integrators debugging congestion and macro floorplans

• Interview prep for implementation / PD / timing closure roles

How this differs from RTL course content

• RTL Design (/topics/rtl) — Verilog, FSM, buses, designer-view STA concepts.

• RTL senior physical-awareness — how RTL structure affects PnR (RTL engineer lens).

• This course — implementation tool flow, closure playbooks, signoff metrics (PD engineer lens).

Related topics

• RTL course — STA introduction

• PD-aware RTL (senior)

• RTL for timing closure

RTL → GDSII flow

RTL + constraints
    │
    ▼
 Synthesis (netlist, mapped cells, initial timing)
    │
    ▼
 Floorplan (die, macros, power grid, blockages, pins)
    │
    ▼
 Placement (global → detailed, congestion, legalize)
    │
    ▼
 CTS (skew, latency, clock gating, hold buffer insertion)
    │
    ▼
 Routing (global → detailed, antenna, shielding)
    │
    ▼
 STA signoff (multi-corner, OCV, ECO)
    │
    ▼
 Power signoff (IR, EM) + PV (DRC, LVS, fill)
    │
    ▼
 Tapeout (GDS, documentation, foundry handoff)

Each stage optimizes different metrics. Timing closure is iterative across placement, CTS, and routing — not a single pass at the end.

8-week study plan (45 min/day)

1. Week 1: how-to-use, flow overview, libraries — skim RTL timing cross-links.

2. Week 2: floorplanning hub + lessons + Q&A aloud.

3. Week 3: placement + congestion debug patterns.

4. Week 4: CTS + routing — skew vs hold narratives.

5. Week 5: timing closure playbook + multi-corner signoff.

6. Week 6: power signoff + physical verification.

7. Week 7: tapeout checklist + closure metrics dashboard.

8. Week 8: interview scenarios + cheatsheet + mock timing storm.

Closure narrative framework

METRIC → HYPOTHESIS → EXPERIMENT → FIX → REGRESSION

  METRIC:     WNS/TNS, DRV count, congestion map, IR hotspot, DRC cluster
  HYPOTHESIS: ordered likely causes (wrong corner, clock, grid, route)
  EXPERIMENT: one report or map before changing anything
  FIX:        minimal ECO — buffer, layer, blockage, constraint
  REGRESSION: corners/modes you must re-run; what cannot regress

Course outline (sections coming in later phases)

1. how-to-use — pacing, prerequisites, study rhythm

2. pd-flow-overview — stage inputs/outputs and ownership

3. data-and-libraries — LEF, DEF, liberty, tech file, corners

4. floorplanning — die size, macros, power plan, pins

5. placement — congestion, legalization, hierarchy

6. clock-tree-synthesis — skew, latency, gating, multi-clock

7. routing — layers, antenna, shielding

8. timing-closure — SDC, setup/hold, ECO, crosstalk

9. power-signoff — IR, EM, UPF implementation

10. physical-verification — DRC, LVS, fill, waivers

11. signoff-tapeout — metrics, checklist, handoff, post-mask ECO

12. interview-prep — scenarios and senior Q&A bank

13. cheatsheet — one-page closure patterns

Key takeaways

• PD interviews reward structured closure narratives, not tool trivia.

• Always name the metric and corner before proposing a fix.

• Cross-link RTL lessons for theory; this course is implementation closure.

Common pitfalls

• Tweaking placement without reading congestion map — wastes iterations.

• Closing setup at one corner while hold fails at another — incomplete signoff.

• Ignoring power grid until IR fails late — expensive rework.

Detailed section notes

Interview performance is structured closure thinking under time pressure.

Reports and artifacts to inspect

• one-slide metric dashboard for the scenario

• hypothesis list sorted by likelihood and cost

• one report/map per experiment

• regression list after the proposed fix

Mini case study

A strong answer to any scenario starts with the failing metric and signoff context. A weak answer starts with a tool command or random optimization knob.

Debug branches

• If you are stuck, restate the metric and ask for corner/mode/stage.

• If multiple failures exist, separate hard gates from tracked risks.

• If pressured to waive, describe approval path and silicon risk.

Senior review question

Ask yourself: what single report line would prove this page's concept is either passing or failing?

What changes at 10+ years

• You are expected to predict what your fix can break before running it.

• You should recognize when the issue is methodology, not one block's implementation.

• You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

Principal-level review bar

Hub pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

What excellent looks like

• Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

• Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

• Chooses experiments by information gain and reversibility, not by habit.

• States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

• Turns recurring failures into methodology guardrails, dashboards, or checklist items.

Closure note template

STAFF / PRINCIPAL CLOSURE NOTE

Context:
  stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
  tag: <database / netlist / SDC / library stack>
  failing metric: <exact report line>
  affected scope: <block / hierarchy / path group / power domain / region>

Hypotheses:
  H1: <most likely physical or constraint mechanism>
  H2: <competing explanation>
  H3: <methodology or input-data issue>

Decision:
  next experiment: <cheap check that can falsify H1>
  fix candidate: <minimal reversible change>
  rollback trigger: <metric that says the fix is wrong>
  regression set: <timing / route / power / PV / DFT / package>
  escalation owner: <team or reviewer>

Tradeoffs a senior engineer must discuss

Technical tradeoff

Interview performance is structured closure thinking under time pressure. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

Cross-team tradeoff

• What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

• Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

• What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

Leadership communication

"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

Key takeaways

• Always connect the concept back to a measurable signoff artifact.

• A fix is not complete until you can name the regression checks.

Common pitfalls

• Optimizing by habit instead of reading the current report.

• Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.