Cache Coherency · All levels

ReadShared and ReadUnique Flows: Mechanism

Mechanism for ReadShared and ReadUnique Flows.

Mechanism to understand

Mechanism for ReadShared and ReadUnique Flows explains how to reason from coherency invariant to measurable engineering decision.

Read intent determines whether sharers are preserved or invalidated, directly shaping downstream latency and interference.

  • Start from invariant, not from one signal waveform.

  • Track ownership and sharer intent as first-class state.

  • Keep ordering assumptions explicit in every review.

Reference flow

diagram
COHERENCY DECISION FLOW — ReadShared and ReadUnique Flows

request intent (read/shared/unique/writeback/evict)
      |
      v
ownership check + sharer metadata evaluation
      |
      v
snoop / directory action + ordering gate
      |
      v
data source selection (owner forward vs memory)
      |
      v
state transition + acknowledgment closure
      |
      v
metric validation + regression guardrails

Cache coherency deep dive

Cache coherence is a correctness contract across caches, interconnect, and software ordering.

Concept diagram

diagram
requester -> coherence fabric -> owner or memory -> state update

Metric graph

diagram
traffic mix across request, snoop, response, data

Metrics and artifacts to collect

  • coherence latency

  • invalidation rate

  • retry rate

  • stale-read incidents

Mini case study

Anchor debug to first stale read and the exact line state transition.

Debug branches

  • Track ownership

  • Track ordering

  • Track evidence

Senior review question

Ask: what is the first line state transition that deviates, and which ordering rule does it break?

Key takeaways

  • Tie every coherency claim to one cache line, one transaction identity, and one measurable counter.

  • Keep proof artifacts from simulation and silicon replay aligned by address, state, and ordering event.

Common pitfalls

  • Chasing bandwidth regressions without checking false sharing and line bouncing first.

  • Assuming coherence correctness implies memory consistency correctness.

  • Declaring closure without litmus, stress, and post-silicon replay evidence.