Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutRoadmapCareersInternshipsFAQContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Reading Path
  • Cache Coherency Glossary
  • The Shared Course Model
  • Cache Coherency Revision Sheet
  • Why Coherence Exists8
  • States and Protocols12
  • Transactions12
    • Read and Write-Permission Flows
    • Forwarding Versus Memory Sourcing
      • Who May Supply Data?
      • Dirty Intervention
      • Three-Hop Versus Four-Hop
      • When Memory Is Stale
    • Writeback, Eviction and Cleaning
  • Races and Controller Design8
  • Progress and the Fabric16
  • Ordering and Synchronization12
  • Performance and Scalability12
  • Real Protocols12
  • SoC Integration12
  • Power, Clocking and Reliability12
  • Verification12
  • Debug and Bring-up12
  • Interview and Design Review17
  • Capstone: A Coherent Model Lab5
Loading lesson

←Forwarding Versus Memory Sourcing
  1. Topics
  2. Cache Coherency
  3. Transactions
  4. Forwarding Versus Memory Sourcing
  5. When Memory Is Stale
On this page

    Part 3 of 14, lesson 8 of 12Part 3 of 14/Transactions/Lesson 8 of 12All levels

    When Memory Is Stale

    Distinguish legally stale memory from an illegal stale response, and keep the newest value safe in pending buffers.

    When does old memory become a bug?

    Memory can legally lag a write-back cache. The error is returning its old value when the line's history requires the newer one. Review The Data-Value Invariant rather than using agreement with memory as the reference.

    In each independent case below, X started at 0 and C0's last store wrote 5. No later store occurred. The rows are snapshots, not a sequence.

    Case

    C0 state / value

    C1 state / value

    H directory

    Memory

    Newest data

    MESI, dirty exclusive

    M / 5

    I / -

    exclusive(C0)

    0

    C0: 5

    MOESI, dirty shared

    O / 5

    S / 5

    O: C0, sharers {C1}

    0

    C0 and C1: 5

    Pending transfer, Data at H

    I / -

    IM^D / -

    exclusive(C0), pend GetM C1

    0

    H buffer: 5

    Incorrect refill

    I / -

    M / 0

    exclusive(C1)

    0

    none: the newest value 5 was lost

    MSI, settled sharing

    S / 5

    S / 5

    S{C0,C1}

    5

    C0, C1 and memory: 5

    Case

    Verdict

    MESI, dirty exclusive

    Legal: memory stale, C0 is responsible

    MOESI, dirty shared

    Legal: memory stale, C0 (O) is responsible

    Pending transfer, Data at H

    Legal while pending: H must grant 5, not memory's 0

    Incorrect refill

    Bug: C1 was granted memory's stale 0

    MSI, settled sharing

    Legal: memory current

    Decision tree separating legally stale memory from a stale response and from loss of the only newest value.
    Judge the value a requester received and where the newest value lives, not memory's value alone.

    Track the newest value through every step

    The pending-transfer row has no usable cache copy, but it is not U. H holds the newest data and has not finished the transfer. Replacing its pending record with U would let a new request read 0 from memory. A pending entry must therefore remember both the permission work and where the newest data is.

    In the incorrect-refill row SWMR still holds: C1 is the only writable cache. Correct permissions cannot excuse installing 0 after losing 5. Conversely, comparing a cache's 5 with memory's 0 would wrongly reject the legal exclusive row. A checker must compare each value returned against the order of stores, not against memory.

    Clearing a transaction because every Inv-Ack has arrived while the dirty data it accepted still has nowhere safe to go. The permission work can finish before the data has reached its destination.

    Give a legal stale-memory example and an illegal stale-response example with the same memory value. Name the history that makes the second one wrong.

    Check yourself Why is the pending-transfer row different from U even though neither cache has a readable copy?

    U means no cache holds X and no work is pending, so memory is current. Here H's buffer holds 5, memory holds 0 and the transfer is outstanding. Recording U would lose the newest value.

    Related topics

    • Shared course model

    • Follow the newest value step by step

    Previous

    33 / 167

    Next: Writeback, Eviction and Cleaning

    Up next

    Up nextWriteback, Eviction and Cleaning

    Sign in to save progress

    Practice this lessonPrevious lessonReport an error

    See also

    • Who May Supply Data?
    • Dirty Intervention